37b8b96683
instruction.rs: Clarify the purpose of Insn
2023-04-29 23:34:28 -05:00
96b6038bbe
Chirp: Bus Schism: Split into Mem (internal) and Screen (external)
2023-04-29 23:32:14 -05:00
f4d7e514bc
auto_cast: Move out of bus module
2023-04-29 19:52:38 -05:00
beab7c968b
Fix copy paste errors and read-out-of-bounds check
2023-04-29 18:44:00 -05:00
33b6d0218e
cpu/tests: Test invalid instructions more exhaustively
2023-04-29 18:43:08 -05:00
4ec9e2cb71
cpu/behavior: Tag each Insn implementation
2023-04-29 18:39:44 -05:00
8b4d5be49d
tests: Update tests for memory being CPU-internal
2023-04-29 18:38:38 -05:00
cb69af048f
cpu: Change ST and DT back to u8
2023-04-29 18:37:29 -05:00
57c2ac681c
cpu: fix renaming mistake "screen" -> "mem"
2023-04-29 18:34:24 -05:00
ea357be477
Monotonic: This flag is being deprecated soon, switch it for bool
2023-04-29 18:20:49 -05:00
7d5718f384
cpu.rs: Separate lastkey from flags
2023-04-29 12:08:26 -05:00
16a5e6a2a4
cpu.rs: Actually derive (De)Serialize if feature=serde
2023-04-23 12:16:31 -05:00
04736f1153
mode.rs: Implement more traits for use in frontend
2023-04-23 12:14:46 -05:00
59ba8ac20b
bus/read.rs: Improve template code somewhat
2023-04-23 12:14:04 -05:00
c1219e60f0
cpu.rs: Refactor for modularity
...
- Break into submodules
- Move bus into submodule of CPU
- Keep program and charset rom inside CPU
- Take only the screen on the external Bus
- Refactor the disassembler into an instruction definition and the actual "Dis" item
2023-04-23 12:10:02 -05:00
92dc899510
Update copyright notices
2023-04-23 11:58:57 -05:00
1c1d4dafaf
cpu.rs: Adjust doctests for new stack behavior
2023-04-17 06:39:05 -05:00
45adf0a2b8
cpu.rs: Remove stack from main memory
2023-04-17 06:34:48 -05:00
e842755d77
quirks: Fix description for screen_wrap
2023-04-17 05:39:18 -05:00
88693f6c72
screens: Fix last-byte-bug in regression test cases
2023-04-17 05:27:23 -05:00
381b2a69bd
tests: load_region asserts that all data must be copied
2023-04-17 05:26:49 -05:00
1573e00928
instruction.rs: Add edge wrapping for draw_lores_sprite, and fix the Last Byte Bug
2023-04-17 05:15:12 -05:00
95d4751cdd
bus: Major refactor: auto-impl implicit casting for all numerics
2023-04-17 05:12:37 -05:00
7d25a9f5f1
quirks.rs: Prepare screen_wrap quirk for future xochip compat
2023-04-17 05:09:16 -05:00
43fa623da3
Improve workflow and docs somewhat, make minifb optional
2023-04-14 22:20:30 -05:00
674af62465
cpu.rs: Break into submodules
2023-04-14 21:25:41 -05:00
78a5a9790a
Misc: clean up in preparation for merge
2023-04-14 16:33:54 -05:00
8bb34f2593
schip: Improve architecture & compatibility somewhat
2023-04-03 05:46:33 -05:00
acc7629516
schip: Add preliminary SuperChip support (no test)
2023-04-03 02:01:25 -05:00
03a6934a59
tests.rs: BC_test tests flawed behavior.
2023-04-02 14:47:33 -05:00
83cc35c968
Move submodules to project root
2023-04-02 14:45:32 -05:00
89f66c3d5b
Add chip8Archive as a submodule, for testing
2023-04-02 14:21:43 -05:00
f27537b3b8
tests: Update tests to match current behavior.
2023-04-01 02:31:51 -05:00
bb8015f33c
Quirks: Make the Cosmac VIP behavior default.
2023-04-01 00:15:40 -05:00
7173b9e39b
Break io into chirp-minifb, and refactor to use Results in more places
2023-04-01 00:14:15 -05:00
a676280ec8
clippy: Fix all clippy lints
2023-03-31 14:32:01 -05:00
c1f457814d
disassembler: 100% line coverage
2023-03-30 08:53:10 -05:00
cc3bc3a7fe
Major Refactor: Make invalid states unrepresentable ™️
...
- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
- Now >10x faster
- Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
- (use option -S to set the number of instructions per epoch)
2023-03-30 08:27:06 -05:00
f60a4b3cc2
Refactor disassembler to use imperative-rs
...
It's like MAGIC. Easily cut out 200 LOC
2023-03-30 02:12:03 -05:00
e54f66f6c4
disassemble.rs: Update function names to match cpu.rs
2023-03-29 23:46:57 -05:00
b9c35c0e68
lib.rs: Deny (missing docs)
2023-03-29 23:45:39 -05:00
ce0dc954d0
tests: Improve cpu.rs line coverage to >99%
2023-03-28 12:31:56 -05:00
83c178413d
tests: Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience.
2023-03-28 08:57:24 -05:00
fbc0a0b2ea
tests: Coverage and cleanup/speedup
...
- Improved test coverage to >80% of lines, functions
- When doctests are included.
- Wrote new unit tests:
- Explicit tests for invalid instructions in the
ranges {`5xyn`, `8xyn`, `9xyn`, `Fxbb`}
- `rand` Tests for 1052671 cycles, to ensure
randomly generated number is < ANDed byte
- `Ex9E` (sek), `ExA1`(snek) will press only the expected key,
then every key except the expected key, for every address
- `Fx0A` (waitk) asserts based on the waveform of a keypress.
After all, an A press is an A press.
- Improved test performance by printing slightly less
- Removed nightly requirement
- (now optional, with feature = "unstable")
- Amended justfile to test with `cargo nextest` (nice)
- Changed release builds to optlevel 3
2023-03-28 07:33:17 -05:00
d5cfdc6802
tests: Move chip8-test-suite to integration tests.
2023-03-27 21:01:33 -05:00
b8720142c7
disassemble.rs: Make asm format more consistent.
2023-03-27 18:31:18 -05:00
0e91b103ed
LICENSE: Add MIT Licence
2023-03-27 18:30:31 -05:00
784845b6f5
cpu.rs: Make quirks individually configurable
2023-03-27 17:27:55 -05:00
a40ee94499
cpu/tests: Add chip8-test-suite, organize tests
2023-03-27 17:21:23 -05:00
4b5de191d8
cpu/tests.rs: Use instruction function directly in non-parser tests
2023-03-26 19:04:36 -05:00
