Refactor disassembler to use imperative-rs
It's like MAGIC. Easily cut out 200 LOC
This commit is contained in:
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22
Cargo.lock
generated
22
Cargo.lock
generated
@ -182,6 +182,7 @@ version = "0.1.0"
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dependencies = [
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"gumdrop",
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"iced",
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"imperative-rs",
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"minifb",
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"owo-colors",
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"rand",
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@ -1086,6 +1087,27 @@ version = "1.0.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39"
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[[package]]
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name = "imperative-rs"
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version = "0.3.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "fed4f0a3a8fe169e919b74f6ba77c473d356ef05d0d65da06467b8836e508aa3"
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dependencies = [
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"imperative-rs-derive",
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]
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[[package]]
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name = "imperative-rs-derive"
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version = "0.3.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "02b842fd8a24b2b715ac0baffae4aa72aa59ecb8e90d3de175180dbb5b1caaab"
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dependencies = [
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"lazy_static",
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"proc-macro2",
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"quote",
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"syn 1.0.109",
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]
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[[package]]
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name = "indexmap"
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version = "1.9.3"
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@ -28,6 +28,7 @@ overflow-checks = false
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[dependencies]
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gumdrop = "^0.8.1"
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iced = {version = "0.8.0", optional = true}
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imperative-rs = "0.3.1"
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minifb = { version = "^0.24.0", features = ["wayland"] }
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owo-colors = "^3"
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rand = "^0.8.5"
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@ -1,7 +1,7 @@
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use chirp::{error::Result, prelude::*};
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use chirp::{cpu::Disassembler, error::Result, prelude::*};
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use gumdrop::*;
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use std::{fs::read, path::PathBuf};
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use owo_colors::OwoColorize;
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use std::{fs::read, path::PathBuf};
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#[derive(Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Options, Hash)]
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struct Arguments {
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@ -22,18 +22,20 @@ fn parse_hex(value: &str) -> std::result::Result<u16, std::num::ParseIntError> {
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fn main() -> Result<()> {
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let options = Arguments::parse_args_default_or_exit();
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let contents = &read(&options.file)?;
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let disassembler = Disassemble::default();
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let disassembler = Dis::default();
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for (addr, insn) in contents[options.offset..].chunks_exact(2).enumerate() {
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let insn = u16::from_be_bytes(
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insn.try_into()
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.expect("Iterated over 2-byte chunks, got <2 bytes"),
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);
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println!(
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"{:03x}: {} {:04x}",
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2 * addr + 0x200 + options.offset,
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disassembler.instruction(insn),
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insn.bright_black(),
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"{}",
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format_args!(
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"{:03x}: {} {:04x}",
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2 * addr + 0x200 + options.offset,
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disassembler.once(insn),
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insn.bright_black(),
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)
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);
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}
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Ok(())
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@ -104,7 +104,7 @@ impl State {
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0x50,
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0x200,
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0xefe,
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Disassemble::default(),
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Dis::default(),
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options.breakpoints,
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ControlFlags {
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quirks: chirp::cpu::Quirks {
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21
src/cpu.rs
21
src/cpu.rs
@ -6,9 +6,16 @@
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#[cfg(test)]
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mod tests;
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pub mod disassemble;
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/// Disassembles Chip-8 instructions
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pub trait Disassembler {
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/// Disassemble a single instruction
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fn once(&self, insn: u16) -> String;
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}
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use self::disassemble::Disassemble;
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pub mod disassembler;
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pub mod old_disassembler;
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use self::disassembler::Dis;
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use crate::bus::{Bus, Read, Region, Write};
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use owo_colors::OwoColorize;
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use rand::random;
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@ -138,7 +145,7 @@ pub struct CPU {
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timer: Instant,
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cycle: usize,
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breakpoints: Vec<Adr>,
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disassembler: Disassemble,
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disassembler: Dis,
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}
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// public interface
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@ -164,7 +171,7 @@ impl CPU {
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font: Adr,
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pc: Adr,
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sp: Adr,
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disassembler: Disassemble,
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disassembler: Dis,
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breakpoints: Vec<Adr>,
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flags: ControlFlags,
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) -> Self {
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@ -549,7 +556,7 @@ impl CPU {
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self.pc = self.pc.wrapping_add(2);
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// decode opcode
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use disassemble::{a, b, i, n, x, y};
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use old_disassembler::{a, b, i, n, x, y};
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let (i, x, y, n, b, a) = (
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i(opcode),
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x(opcode),
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@ -674,7 +681,7 @@ impl CPU {
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"{:3} {:03x}: {:<36}{:?}",
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self.cycle.bright_black(),
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pc,
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self.disassembler.instruction(opcode),
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self.disassembler.once(opcode),
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elapsed.dimmed()
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);
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}
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@ -765,7 +772,7 @@ impl Default for CPU {
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},
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timer: Instant::now(),
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breakpoints: vec![],
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disassembler: Disassemble::default(),
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disassembler: Dis::default(),
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}
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}
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}
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184
src/cpu/disassembler.rs
Normal file
184
src/cpu/disassembler.rs
Normal file
@ -0,0 +1,184 @@
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//! A disassembler for Chip-8 opcodes
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use super::Disassembler;
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use imperative_rs::InstructionSet;
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use owo_colors::{OwoColorize, Style};
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use std::fmt::Display;
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#[allow(non_camel_case_types, non_snake_case, missing_docs)]
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#[derive(Clone, Copy, InstructionSet, PartialEq, Eq, PartialOrd, Ord, Hash)]
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/// Implements a Disassembler using imperative_rs
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pub enum Insn {
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/// | 00e0 | Clear screen memory to 0s
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#[opcode = "0x00e0"]
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cls,
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/// | 00ee | Return from subroutine
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#[opcode = "0x00ee"]
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ret,
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/// | 1aaa | Jumps to an absolute address
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#[opcode = "0x1AAA"]
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jmp { A: u16 },
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/// | 2aaa | Pushes pc onto the stack, then jumps to a
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#[opcode = "0x2AAA"]
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call { A: u16 },
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/// | 3xbb | Skips next instruction if register X == b
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#[opcode = "0x3xBB"]
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seb { B: u8, x: usize },
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/// | 4xbb | Skips next instruction if register X != b
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#[opcode = "0x4xBB"]
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sneb { B: u8, x: usize },
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/// | 9XY0 | Skip next instruction if vX == vY |
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#[opcode = "0x5xy0"]
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se { y: usize, x: usize },
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/// | 6xbb | Loads immediate byte b into register vX
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#[opcode = "0x6xBB"]
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movb { B: u8, x: usize },
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/// | 7xbb | Adds immediate byte b to register vX
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#[opcode = "0x7xBB"]
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addb { B: u8, x: usize },
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/// | 8xy0 | Loads the value of y into x
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#[opcode = "0x8xy0"]
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mov { x: usize, y: usize },
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/// | 8xy1 | Performs bitwise or of vX and vY, and stores the result in vX
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#[opcode = "0x8xy1"]
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or { y: usize, x: usize },
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/// | 8xy2 | Performs bitwise and of vX and vY, and stores the result in vX
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#[opcode = "0x8xy2"]
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and { y: usize, x: usize },
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/// | 8xy3 | Performs bitwise xor of vX and vY, and stores the result in vX
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#[opcode = "0x8xy3"]
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xor { y: usize, x: usize },
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/// | 8xy4 | Performs addition of vX and vY, and stores the result in vX
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#[opcode = "0x8xy4"]
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add { y: usize, x: usize },
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/// | 8xy5 | Performs subtraction of vX and vY, and stores the result in vX
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#[opcode = "0x8xy5"]
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sub { y: usize, x: usize },
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/// | 8xy6 | Performs bitwise right shift of vX (or vY)
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#[opcode = "0x8xy6"]
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shr { y: usize, x: usize },
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/// | 8xy7 | Performs subtraction of vY and vX, and stores the result in vX
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#[opcode = "0x8xy7"]
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bsub { y: usize, x: usize },
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/// | 8xyE | Performs bitwise left shift of vX
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#[opcode = "0x8xye"]
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shl { y: usize, x: usize },
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/// | 9XY0 | Skip next instruction if vX != vY
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#[opcode = "0x9xy0"]
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sne { y: usize, x: usize },
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/// | Aaaa | Load address #a into register I
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#[opcode = "0xaAAA"]
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movI { A: usize },
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/// | Baaa | Jump to &adr + v0
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#[opcode = "0xbAAA"]
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jmpr { A: usize },
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/// | Cxbb | Stores a random number & the provided byte into vX
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#[opcode = "0xcxBB"]
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rand { B: u8, x: usize },
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/// | Dxyn | Draws n-byte sprite to the screen at coordinates (vX, vY)
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#[opcode = "0xdxyn"]
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draw { x: usize, y: usize, n: u8 },
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/// | eX9e | Skip next instruction if key == vX
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#[opcode = "0xex9e"]
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sek { x: usize },
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/// | eXa1 | Skip next instruction if key != vX
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#[opcode = "0xexa1"]
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snek { x: usize },
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// | fX07 | Set vX to value in delay timer
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#[opcode = "0xfx07"]
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getdt { x: usize },
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// | fX0a | Wait for input, store key in vX
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#[opcode = "0xfx0a"]
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waitk { x: usize },
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// | fX15 | Set sound timer to the value in vX
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#[opcode = "0xfx15"]
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setdt { x: usize },
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// | fX18 | set delay timer to the value in vX
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#[opcode = "0xfx18"]
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movst { x: usize },
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// | fX1e | Add vX to I
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#[opcode = "0xfx1e"]
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addI { x: usize },
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// | fX29 | Load sprite for character x into I
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#[opcode = "0xfx29"]
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font { x: usize },
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// | fX33 | BCD convert X into I[0..3]
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#[opcode = "0xfx33"]
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bcd { x: usize },
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// | fX55 | DMA Stor from I to registers 0..X
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#[opcode = "0xfx55"]
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dmao { x: usize },
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// | fX65 | DMA Load from I to registers 0..X
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#[opcode = "0xfx65"]
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dmai { x: usize },
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}
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impl Display for Insn {
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#[rustfmt::skip]
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fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
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match self {
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Insn::cls => write!(f, "cls "),
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Insn::ret => write!(f, "ret "),
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Insn::jmp { A } => write!(f, "jmp {A:03x}"),
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Insn::call { A } => write!(f, "call {A:03x}"),
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Insn::seb { B, x } => write!(f, "se #{B:02x}, v{x:X}"),
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Insn::sneb { B, x } => write!(f, "sne #{B:02x}, v{x:X}"),
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Insn::se { y, x } => write!(f, "se v{x:X}, v{y:X}"),
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Insn::movb { B, x } => write!(f, "mov #{B:02x}, v{x:X}"),
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Insn::addb { B, x } => write!(f, "add #{B:02x}, v{x:X}"),
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Insn::mov { x, y } => write!(f, "mov v{y:X}, v{x:X}"),
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Insn::or { y, x } => write!(f, "or v{y:X}, v{x:X}"),
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Insn::and { y, x } => write!(f, "and v{y:X}, v{x:X}"),
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Insn::xor { y, x } => write!(f, "xor v{y:X}, v{x:X}"),
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Insn::add { y, x } => write!(f, "add v{y:X}, v{x:X}"),
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Insn::sub { y, x } => write!(f, "sub v{y:X}, v{x:X}"),
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Insn::shr { y, x } => write!(f, "shr v{y:X}, v{x:X}"),
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Insn::bsub { y, x } => write!(f, "bsub v{y:X}, v{x:X}"),
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Insn::shl { y, x } => write!(f, "shl v{y:X}, v{x:X}"),
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Insn::sne { y, x } => write!(f, "sne v{x:X}, v{y:X}"),
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Insn::movI { A } => write!(f, "mov ${A:03x}, I"),
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Insn::jmpr { A } => write!(f, "jmp ${A:03x}+v0"),
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Insn::rand { B, x } => write!(f, "rand #{B:02x}, v{x:X}"),
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Insn::draw { x, y, n } => write!(f, "draw #{n:x}, v{x:X}, v{y:X}"),
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Insn::sek { x } => write!(f, "sek v{x:X}"),
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Insn::snek { x } => write!(f, "snek v{x:X}"),
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Insn::getdt { x } => write!(f, "mov DT, v{x:X}"),
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Insn::waitk { x } => write!(f, "waitk v{x:X}"),
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Insn::setdt { x } => write!(f, "mov v{x:X}, DT"),
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Insn::movst { x } => write!(f, "mov v{x:X}, ST"),
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Insn::addI { x } => write!(f, "add v{x:X}, I"),
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Insn::font { x } => write!(f, "font v{x:X}, I"),
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Insn::bcd { x } => write!(f, "bcd v{x:X}, &I"),
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Insn::dmao { x } => write!(f, "dmao v{x:X}"),
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Insn::dmai { x } => write!(f, "dmai v{x:X}"),
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}
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}
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}
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/// Disassembles Chip-8 instructions, printing them in the provided [owo_colors::Style]s
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#[derive(Clone, Copy, Debug, PartialEq)]
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pub struct Dis {
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/// Styles invalid instructions
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pub invalid: Style,
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/// Styles valid instruction
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pub normal: Style,
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}
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impl Default for Dis {
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fn default() -> Self {
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Self {
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invalid: Style::new().bold().red(),
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normal: Style::new().green(),
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}
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}
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}
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impl Disassembler for Dis {
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fn once(&self, insn: u16) -> String {
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if let Some((_, insn)) = Insn::decode(&insn.to_be_bytes()).ok() {
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format!("{}", insn.style(self.normal))
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} else {
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format!("{}", format_args!("inval {insn:04x}").style(self.invalid))
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}
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}
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}
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@ -3,7 +3,7 @@
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//! A disassembler for Chip-8 opcodes
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use super::{Adr, Nib, Reg};
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use super::{Adr, Disassembler, Nib, Reg};
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use owo_colors::{OwoColorize, Style};
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type Ins = Nib;
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@ -40,22 +40,22 @@ pub fn a(ins: u16) -> Adr {
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/// Disassembles Chip-8 instructions, printing them in the provided [owo_colors::Style]s
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#[derive(Clone, Debug, PartialEq)]
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pub struct Disassemble {
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pub struct DeprecatedDisassembler {
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invalid: Style,
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normal: Style,
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}
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impl Default for Disassemble {
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impl Default for DeprecatedDisassembler {
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fn default() -> Self {
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Disassemble::builder().build()
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DeprecatedDisassembler::builder().build()
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}
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}
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// Public API
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impl Disassemble {
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impl DeprecatedDisassembler {
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/// Returns a new Disassemble with the provided Styles
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pub fn new(invalid: Style, normal: Style) -> Disassemble {
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Disassemble { invalid, normal }
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pub fn new(invalid: Style, normal: Style) -> DeprecatedDisassembler {
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DeprecatedDisassembler { invalid, normal }
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}
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/// Creates a [DisassembleBuilder], for partial configuration
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pub fn builder() -> DisassembleBuilder {
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@ -183,8 +183,14 @@ impl Disassemble {
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}
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}
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impl Disassembler for DeprecatedDisassembler {
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fn once(&self, insn: u16) -> String {
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self.instruction(insn)
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}
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}
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// Private api
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impl Disassemble {
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impl DeprecatedDisassembler {
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/// Unused instructions
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fn unimplemented(&self, opcode: u16) -> String {
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format!("inval {opcode:04x}")
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@ -400,8 +406,8 @@ impl DisassembleBuilder {
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self
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}
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/// Builds a Disassemble
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pub fn build(self) -> Disassemble {
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Disassemble {
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pub fn build(self) -> DeprecatedDisassembler {
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DeprecatedDisassembler {
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invalid: if let Some(style) = self.invalid {
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style
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} else {
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@ -19,7 +19,7 @@ pub mod prelude {
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use super::*;
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pub use crate::bus;
|
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pub use bus::{Bus, Read, Region::*, Write};
|
||||
pub use cpu::{disassemble::Disassemble, ControlFlags, CPU};
|
||||
pub use cpu::{disassembler::Dis, ControlFlags, CPU};
|
||||
pub use error::Result;
|
||||
pub use io::{UIBuilder, *};
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user