5b5c5b41ab
chirp: Update chirp for changes in cpu.rs
2023-04-23 12:15:36 -05:00
04736f1153
mode.rs: Implement more traits for use in frontend
2023-04-23 12:14:46 -05:00
59ba8ac20b
bus/read.rs: Improve template code somewhat
2023-04-23 12:14:04 -05:00
e9f8d917a4
chirp-imgui: First prototype, using pixels demo as base
2023-04-23 12:13:22 -05:00
c1219e60f0
cpu.rs: Refactor for modularity
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- Break into submodules
- Move bus into submodule of CPU
- Keep program and charset rom inside CPU
- Take only the screen on the external Bus
- Refactor the disassembler into an instruction definition and the actual "Dis" item
2023-04-23 12:10:02 -05:00
33da1089a2
AnyRange: Add AnyRange for taking any range in error
2023-04-23 12:01:47 -05:00
92dc899510
Update copyright notices
2023-04-23 11:58:57 -05:00
3839e90b15
chip8Archive: Update Submodule (adds wdl and octojam9!)
2023-04-18 22:44:47 -05:00
1c1d4dafaf
cpu.rs: Adjust doctests for new stack behavior
2023-04-17 06:39:05 -05:00
0113dd95f6
ui.rs: Refactor debug screen dump: dumps to pwd with good name
2023-04-17 06:35:16 -05:00
45adf0a2b8
cpu.rs: Remove stack from main memory
2023-04-17 06:34:48 -05:00
e842755d77
quirks: Fix description for screen_wrap
2023-04-17 05:39:18 -05:00
88693f6c72
screens: Fix last-byte-bug in regression test cases
2023-04-17 05:27:23 -05:00
381b2a69bd
tests: load_region asserts that all data must be copied
2023-04-17 05:26:49 -05:00
1573e00928
instruction.rs: Add edge wrapping for draw_lores_sprite, and fix the Last Byte Bug
2023-04-17 05:15:12 -05:00
401b247c05
cpu: Remove reference to nonexistent "init" module
2023-04-17 05:13:41 -05:00
95d4751cdd
bus: Major refactor: auto-impl implicit casting for all numerics
2023-04-17 05:12:37 -05:00
7d25a9f5f1
quirks.rs: Prepare screen_wrap quirk for future xochip compat
2023-04-17 05:09:16 -05:00
bafb576705
chip8-test-suite: Update to 4.0
2023-04-17 05:04:23 -05:00
d54fb7eb2c
Merge pull request 'v0.1.1 Partial Super Chip Support' ( #11 ) from schip into main
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Reviewed-on: #11
2023-04-15 04:00:40 +00:00
43fa623da3
Improve workflow and docs somewhat, make minifb optional
2023-04-14 22:20:30 -05:00
674af62465
cpu.rs: Break into submodules
2023-04-14 21:25:41 -05:00
ae32d77757
readme.md: Update readme to indicate partial schip support
2023-04-14 21:00:27 -05:00
973811ee8d
csv: print multiple shots at a time
2023-04-14 21:00:08 -05:00
4f6f91b69b
bus.rs: Debug print screen with drawille, if enabled
2023-04-14 20:58:28 -05:00
d12f3fe710
cpu.rs: Fiddle with the alignment, to help me feel whole.
2023-04-14 16:50:32 -05:00
78a5a9790a
Misc: clean up in preparation for merge
2023-04-14 16:33:54 -05:00
946a6031fb
tests: Update test to match new expected behavior
2023-04-03 05:47:42 -05:00
9bdc418a00
ui.rs: Implement dynamic resolution changing, revert colors for now
2023-04-03 05:47:13 -05:00
8bb34f2593
schip: Improve architecture & compatibility somewhat
2023-04-03 05:46:33 -05:00
9fcae555ce
chirp-minifb: Add quirk toggles back in
2023-04-03 05:45:22 -05:00
acc7629516
schip: Add preliminary SuperChip support (no test)
2023-04-03 02:01:25 -05:00
081dda9c8a
Generate flamegraphs
2023-04-02 15:29:34 -05:00
93bbf67433
cpu.rs: Double max IPF in dynamic timing by only getting the time once
2023-04-02 14:48:34 -05:00
03a6934a59
tests.rs: BC_test tests flawed behavior.
2023-04-02 14:47:33 -05:00
40cc81181b
chip8_test_suite.rs: Load program only once
2023-04-02 14:46:39 -05:00
83cc35c968
Move submodules to project root
2023-04-02 14:45:32 -05:00
89f66c3d5b
Add chip8Archive as a submodule, for testing
2023-04-02 14:21:43 -05:00
f27537b3b8
tests: Update tests to match current behavior.
2023-04-01 02:31:51 -05:00
a4c548d0ec
lib.rs: Remove crate::prelude, re-export in lib.rs
2023-04-01 02:31:06 -05:00
bb8015f33c
Quirks: Make the Cosmac VIP behavior default.
2023-04-01 00:15:40 -05:00
7173b9e39b
Break io into chirp-minifb, and refactor to use Results in more places
2023-04-01 00:14:15 -05:00
3cc3aa534c
Remove Cargo.lock and add to .gitignore
2023-03-31 19:10:24 -05:00
a744fa08c7
Merge branch 'imperative-rs'
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Rewrote the disassembler and `cpu::tick()` for code concision and massive speed improvements.
Turns out, getting the current time takes AGES, so if we don't need it, we don't get it.
2023-03-31 14:33:40 -05:00
a676280ec8
clippy: Fix all clippy lints
2023-03-31 14:32:01 -05:00
627511282a
chirp-minifb: Propagate errors up to main
2023-03-30 10:46:35 -05:00
c1f457814d
disassembler: 100% line coverage
2023-03-30 08:53:10 -05:00
cc3bc3a7fe
Major Refactor: Make invalid states unrepresentable ™️
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- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
- Now >10x faster
- Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
- (use option -S to set the number of instructions per epoch)
2023-03-30 08:27:06 -05:00
8ab9799913
cpu.rs: Fix some documentation errors
2023-03-30 02:13:59 -05:00
f60a4b3cc2
Refactor disassembler to use imperative-rs
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It's like MAGIC. Easily cut out 200 LOC
2023-03-30 02:12:03 -05:00
