Merge pull request 'v0.1.1 Partial Super Chip Support' (#11) from schip into main
Reviewed-on: #11
This commit is contained in:
commit
d54fb7eb2c
39
Cargo.toml
39
Cargo.toml
@ -1,17 +1,40 @@
|
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[package]
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name = "chirp"
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version = "0.1.0"
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version = "0.1.1"
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edition = "2021"
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ignore = ["justfile", ".gitmodules", "chip8-test-suite", "chip8Archive"]
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default-run = "chirp"
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authors = ["John Breaux"]
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license = "MIT"
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publish = false
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[features]
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default = ["unstable"]
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default = ["unstable", "drawille", "minifb"]
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unstable = []
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drawille = ["dep:drawille"]
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iced = ["dep:iced"]
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minifb = ["dep:minifb"]
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rhexdump = ["dep:rhexdump"]
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serde = ["dep:serde"]
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[[bin]]
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name = "chirp"
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path = "src/bin/chirp-minifb/main.rs"
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required-features = ["minifb"]
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[[bin]]
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name = "chirp-disasm"
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required-features = ["default"]
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[[bin]]
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name = "chirp-iced"
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required-features = ["iced"]
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[[bin]]
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name = "chirp-shot-viewer"
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required-features = ["default", "drawille"]
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# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
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[profile.release]
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opt-level = 3
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@ -26,12 +49,14 @@ overflow-checks = false
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[dependencies]
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gumdrop = "^0.8.1"
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drawille = {version = "0.3.0", optional = true}
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iced = {version = "0.8.0", optional = true}
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imperative-rs = "0.3.1"
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minifb = { version = "^0.24.0", features = ["wayland"] }
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owo-colors = "^3"
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rand = "^0.8.5"
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rhexdump = {version = "^0.1.1", optional = true }
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serde = { version = "^1.0", features = ["derive"], optional = true }
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minifb = { version = "^0.24.0", optional = true }
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gumdrop = "^0.8.1"
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imperative-rs = "0.3.1"
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owo-colors = "^3"
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rand = "^0.8.5"
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thiserror = "^1.0.39"
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13
justfile
13
justfile
@ -7,21 +7,24 @@ rat:
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test:
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cargo nextest run
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chirp:
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cargo run --bin chirp-minifb -- chip8-test-suite/bin/chip8-test-suite.ch8
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run rom:
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cargo run -- '{{rom}}'
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debug rom:
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cargo run -- -d '{{rom}}'
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# Run at 2100000 instructions per frame, and output per-frame runtime statistics
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bench:
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cargo run --bin chirp-minifb --release -- chip8Archive/roms/1dcell.ch8 -xP -s10 -S2100000
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cargo run --release -- chip8Archive/roms/1dcell.ch8 -Ps10 -S2100000 -m xochip
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flame rom:
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CARGO_PROFILE_RELEASE_DEBUG=true cargo flamegraph -F 15300 --open --bin chirp-minifb -- '{{rom}}' -s10
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flamebench:
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CARGO_PROFILE_RELEASE_DEBUG=true cargo flamegraph -F 15300 --open --bin chirp-minifb -- chip8Archive/roms/1dcell.ch8 -xPs10 -S2100000
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CARGO_PROFILE_RELEASE_DEBUG=true cargo flamegraph -F 15300 --open --bin chirp-minifb -- chip8Archive/roms/1dcell.ch8 -Ps10 -S2100000 -m xochip
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cover:
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cargo llvm-cov --open --doctests
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tokei:
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tokei --exclude tests/chip8-test-suite
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tokei --exclude chip8-test-suite --exclude chip8Archive
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@ -6,8 +6,9 @@ I don't know!
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So I wrote this, to see if i can find out.
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## Features:
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- 32 * 64 1bpp pixel display, scaled 16x
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- 64 * 128 1bpp pixel display, scaled 8x
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- Full coverage of the original Chip-8 insn set
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- Partial coverage of the Super Chip-8 extension set
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- 64-bit floating point internal sound/delay timers
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- Pause/Resume
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- Set and unset breakpoints
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@ -65,6 +66,7 @@ Optional arguments:
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## TODO:
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- [ ] Move the screen, stack, charset, and program memory into the CPU
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- [ ] Implement sound
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- [ ] Finish unit tests for "quirks"
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- [ ] Make pausing/unpausing the emulator less messy
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@ -1,24 +1,8 @@
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use chirp::{cpu::Disassembler, error::Result, *};
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use chirp::{error::Result, *};
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use gumdrop::*;
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use owo_colors::OwoColorize;
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use std::{fs::read, path::PathBuf};
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#[derive(Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Options, Hash)]
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struct Arguments {
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#[options(help = "Show help text")]
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help: bool,
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#[options(help = "Load a ROM to run on Chirp", free, required)]
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pub file: PathBuf,
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#[options(help = "Load address (usually 200)", parse(try_from_str = "parse_hex"))]
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pub loadaddr: u16,
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#[options(help = "Start disassembling at offset...")]
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pub offset: usize,
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}
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fn parse_hex(value: &str) -> std::result::Result<u16, std::num::ParseIntError> {
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u16::from_str_radix(value, 16)
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}
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fn main() -> Result<()> {
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let options = Arguments::parse_args_default_or_exit();
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let contents = &read(&options.file)?;
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@ -40,3 +24,19 @@ fn main() -> Result<()> {
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}
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Ok(())
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}
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#[derive(Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Options, Hash)]
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struct Arguments {
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#[options(help = "Show help text")]
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help: bool,
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#[options(help = "Load a ROM to run on Chirp", free, required)]
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pub file: PathBuf,
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#[options(help = "Load address (usually 200)", parse(try_from_str = "parse_hex"))]
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pub loadaddr: u16,
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#[options(help = "Start disassembling at offset...")]
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pub offset: usize,
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}
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fn parse_hex(value: &str) -> std::result::Result<u16, std::num::ParseIntError> {
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u16::from_str_radix(value, 16)
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}
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@ -19,6 +19,23 @@ use std::{
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};
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use ui::*;
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pub fn main() -> Result<()> {
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let options = Arguments::parse_args_default_or_exit();
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let state = State::new(options)?;
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for result in state {
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if let Err(e) = result {
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eprintln!("{}", e.bold().red());
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break;
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}
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}
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Ok(())
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}
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/// Parses a hexadecimal string into a u16
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fn parse_hex(value: &str) -> std::result::Result<u16, std::num::ParseIntError> {
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u16::from_str_radix(value, 16)
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}
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#[derive(Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Options, Hash)]
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struct Arguments {
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#[options(help = "Load a ROM to run on Chirp.", required, free)]
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@ -36,6 +53,13 @@ struct Arguments {
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pub step: Option<usize>,
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#[options(help = "Enable performance benchmarking on stderr (requires -S)")]
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pub perf: bool,
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#[options(
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help = "Run in (Chip8, SChip, XOChip) mode.",
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//parse(from_str = "parse_mode")
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)]
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pub mode: Option<Mode>,
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#[options(
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short = "z",
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help = "Disable setting vF to 0 after a bitwise operation."
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@ -62,7 +86,6 @@ struct Arguments {
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help = "Use SUPER-CHIP style indexed jump, which is indexed relative to v[adr]."
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)]
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pub jumping: bool,
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#[options(
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long = "break",
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help = "Set breakpoints for the emulator to stop at.",
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@ -116,14 +139,8 @@ impl State {
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0xefe,
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Dis::default(),
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options.breakpoints,
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ControlFlags {
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quirks: chirp::cpu::Quirks {
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bin_ops: options.vfreset,
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shift: options.shift,
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draw_wait: options.drawsync,
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dma_inc: options.memory,
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stupid_jumps: options.jumping,
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},
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Flags {
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quirks: options.mode.unwrap_or_default().into(),
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debug: options.debug,
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pause: options.pause,
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monotonic: options.speed,
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@ -131,9 +148,15 @@ impl State {
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},
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),
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},
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ui: UIBuilder::new(64, 32, &options.file).build()?,
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ui: UIBuilder::new(128, 64, &options.file).build()?,
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ft: Instant::now(),
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};
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// Flip the state of the quirks
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state.ch8.cpu.flags.quirks.bin_ops ^= options.vfreset;
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state.ch8.cpu.flags.quirks.dma_inc ^= options.memory;
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state.ch8.cpu.flags.quirks.draw_wait ^= options.drawsync;
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state.ch8.cpu.flags.quirks.shift ^= options.shift;
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state.ch8.cpu.flags.quirks.stupid_jumps ^= options.jumping;
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state.ch8.bus.write(0x1feu16, options.data);
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Ok(state)
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}
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@ -154,9 +177,10 @@ impl State {
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let time = time.elapsed();
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let nspt = time.as_secs_f64() / ticks as f64;
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eprintln!(
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"{ticks},\t{time:.05?},\t{:.4}nspt,\t{}ipf",
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"{ticks},\t{time:.05?},\t{:.4} nspt,\t{} ipf,\t{} mips",
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nspt * 1_000_000_000.0,
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((1.0 / 60.0f64) / nspt).trunc(),
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(1.0 / nspt).trunc() / 1_000_000.0,
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);
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}
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}
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@ -201,20 +225,3 @@ impl Iterator for State {
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Some(Ok(()))
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}
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}
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fn main() -> Result<()> {
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let options = Arguments::parse_args_default_or_exit();
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let state = State::new(options)?;
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for result in state {
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if let Err(e) = result {
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eprintln!("{}", e.bold().red());
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break;
|
||||
}
|
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}
|
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Ok(())
|
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}
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|
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/// Parses a hexadecimal string into a u16
|
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fn parse_hex(value: &str) -> std::result::Result<u16, std::num::ParseIntError> {
|
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u16::from_str_radix(value, 16)
|
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}
|
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|
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@ -56,14 +56,14 @@ impl UIBuilder {
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impl Default for UIBuilder {
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fn default() -> Self {
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UIBuilder {
|
||||
width: 64,
|
||||
height: 32,
|
||||
width: 128,
|
||||
height: 64,
|
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name: Some("Chip-8 Interpreter"),
|
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rom: None,
|
||||
window_options: WindowOptions {
|
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title: true,
|
||||
resize: false,
|
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scale: Scale::X16,
|
||||
scale: Scale::X8,
|
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scale_mode: ScaleMode::AspectRatioStretch,
|
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none: true,
|
||||
..Default::default()
|
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@ -106,12 +106,24 @@ impl FrameBuffer {
|
||||
}
|
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pub fn render(&mut self, window: &mut Window, bus: &Bus) -> Result<()> {
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||||
if let Some(screen) = bus.get_region(Region::Screen) {
|
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// Resizing the buffer does not unmap memory.
|
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// After the first use of high-res mode, this is pretty cheap
|
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(self.width, self.height) = match screen.len() {
|
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256 => (64, 32),
|
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1024 => (128, 64),
|
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_ => {
|
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unimplemented!("Screen must be 64*32 or 128*64");
|
||||
}
|
||||
};
|
||||
self.buffer.resize(self.width * self.height, 0);
|
||||
for (idx, byte) in screen.iter().enumerate() {
|
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for bit in 0..8 {
|
||||
self.buffer[8 * idx + bit] = if byte & (1 << (7 - bit)) as u8 != 0 {
|
||||
self.format.fg
|
||||
} else {
|
||||
self.format.bg
|
||||
// .wrapping_add(0x001104 * (idx / self.width) as u32)
|
||||
// .wrapping_add(0x141000 * (idx & 3) as u32)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -2,6 +2,9 @@ use chirp::{error::Result, *};
|
||||
use std::{env::args, fs::read};
|
||||
|
||||
fn main() -> Result<()> {
|
||||
bus! {Screen [0..0x100] = &read(args().nth(1).unwrap_or("screen_dump.bin".to_string()))?}
|
||||
.print_screen()
|
||||
for screen in args().skip(1).inspect(|screen| println!("{screen}")) {
|
||||
let screen = read(screen)?;
|
||||
bus! {Screen [0..screen.len()] = &screen}.print_screen()?;
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
121
src/bus.rs
121
src/bus.rs
@ -166,6 +166,23 @@ impl Bus {
|
||||
}
|
||||
self
|
||||
}
|
||||
/// Updates an existing named range (Region)
|
||||
/// # Examples
|
||||
/// ```rust
|
||||
///# use chirp::*;
|
||||
///# fn main() -> Result<()> {
|
||||
/// let bus = Bus::new().add_region(Program, 0..1234);
|
||||
/// assert_eq!(1234, bus.len());
|
||||
///# Ok(())
|
||||
///# }
|
||||
/// ```
|
||||
pub fn set_region(&mut self, name: Region, range: Range<usize>) -> &mut Self {
|
||||
self.with_size(range.end);
|
||||
if let Some(region) = self.region.get_mut(name as usize) {
|
||||
*region = Some(range);
|
||||
}
|
||||
self
|
||||
}
|
||||
/// Loads data into a named region
|
||||
/// # Examples
|
||||
/// ```rust
|
||||
@ -307,15 +324,43 @@ impl Bus {
|
||||
pub fn print_screen(&self) -> Result<()> {
|
||||
const REGION: Region = Region::Screen;
|
||||
if let Some(screen) = self.get_region(REGION) {
|
||||
let len_log2 = screen.len().ilog2() / 2;
|
||||
#[allow(unused_variables)]
|
||||
let (width, height) = (2u32.pow(len_log2 - 1), 2u32.pow(len_log2));
|
||||
// draw with the drawille library, if available
|
||||
#[cfg(feature = "drawille")]
|
||||
{
|
||||
use drawille::Canvas;
|
||||
let mut canvas = Canvas::new(width * 8, height);
|
||||
let width = width * 8;
|
||||
screen
|
||||
.iter()
|
||||
.enumerate()
|
||||
.flat_map(|(bytei, byte)| {
|
||||
(0..8)
|
||||
.into_iter()
|
||||
.enumerate()
|
||||
.filter_map(move |(biti, bit)| {
|
||||
if (byte << bit) & 0x80 != 0 {
|
||||
Some(bytei * 8 + biti)
|
||||
} else {
|
||||
None
|
||||
}
|
||||
})
|
||||
})
|
||||
.for_each(|index| canvas.set(index as u32 % (width), index as u32 / (width)));
|
||||
println!("{}", canvas.frame());
|
||||
}
|
||||
#[cfg(not(feature = "drawille"))]
|
||||
for (index, byte) in screen.iter().enumerate() {
|
||||
if index % 8 == 0 {
|
||||
print!("|");
|
||||
if index % width as usize == 0 {
|
||||
print!("{index:03x}|");
|
||||
}
|
||||
print!(
|
||||
"{}",
|
||||
format!("{byte:08b}").replace('0', " ").replace('1', "██")
|
||||
format!("{byte:08b}").replace('0', " ").replace('1', "█")
|
||||
);
|
||||
if index % 8 == 7 {
|
||||
if index % width as usize == width as usize - 1 {
|
||||
println!("|");
|
||||
}
|
||||
}
|
||||
@ -339,7 +384,43 @@ impl Read<u16> for Bus {
|
||||
fn read(&self, addr: impl Into<usize>) -> u16 {
|
||||
let addr: usize = addr.into();
|
||||
if let Some(bytes) = self.memory.get(addr..addr + 2) {
|
||||
u16::from_be_bytes(bytes.try_into().expect("asked for 2 bytes, got != 2 bytes"))
|
||||
u16::from_be_bytes(bytes.try_into().expect("Should get 2 bytes"))
|
||||
} else {
|
||||
0xc5c5
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Read<u32> for Bus {
|
||||
/// Read a u16 from address `addr`
|
||||
fn read(&self, addr: impl Into<usize>) -> u32 {
|
||||
let addr: usize = addr.into();
|
||||
if let Some(bytes) = self.memory.get(addr..addr + 4) {
|
||||
u32::from_be_bytes(bytes.try_into().expect("Should get 4 bytes"))
|
||||
} else {
|
||||
0xc5c5
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Read<u64> for Bus {
|
||||
/// Read a u16 from address `addr`
|
||||
fn read(&self, addr: impl Into<usize>) -> u64 {
|
||||
let addr: usize = addr.into();
|
||||
if let Some(bytes) = self.memory.get(addr..addr + 8) {
|
||||
u64::from_be_bytes(bytes.try_into().expect("Should get 8 bytes"))
|
||||
} else {
|
||||
0xc5c5
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Read<u128> for Bus {
|
||||
/// Read a u16 from address `addr`
|
||||
fn read(&self, addr: impl Into<usize>) -> u128 {
|
||||
let addr: usize = addr.into();
|
||||
if let Some(bytes) = self.memory.get(addr..addr + 16) {
|
||||
u128::from_be_bytes(bytes.try_into().expect("Should get 16 bytes"))
|
||||
} else {
|
||||
0xc5c5
|
||||
}
|
||||
@ -366,6 +447,36 @@ impl Write<u16> for Bus {
|
||||
}
|
||||
}
|
||||
|
||||
impl Write<u32> for Bus {
|
||||
/// Write a u16 to address `addr`
|
||||
fn write(&mut self, addr: impl Into<usize>, data: u32) {
|
||||
let addr: usize = addr.into();
|
||||
if let Some(slice) = self.get_mut(addr..addr + 4) {
|
||||
data.to_be_bytes().as_mut().swap_with_slice(slice);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Write<u64> for Bus {
|
||||
/// Write a u16 to address `addr`
|
||||
fn write(&mut self, addr: impl Into<usize>, data: u64) {
|
||||
let addr: usize = addr.into();
|
||||
if let Some(slice) = self.get_mut(addr..addr + 8) {
|
||||
data.to_be_bytes().as_mut().swap_with_slice(slice);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Write<u128> for Bus {
|
||||
/// Write a u16 to address `addr`
|
||||
fn write(&mut self, addr: impl Into<usize>, data: u128) {
|
||||
let addr: usize = addr.into();
|
||||
if let Some(slice) = self.get_mut(addr..addr + 16) {
|
||||
data.to_be_bytes().as_mut().swap_with_slice(slice);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(target_feature = "rhexdump")]
|
||||
impl Display for Bus {
|
||||
fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result {
|
||||
|
||||
589
src/cpu.rs
589
src/cpu.rs
@ -6,15 +6,18 @@
|
||||
#[cfg(test)]
|
||||
mod tests;
|
||||
|
||||
/// Disassembles Chip-8 instructions
|
||||
pub trait Disassembler {
|
||||
/// Disassemble a single instruction
|
||||
fn once(&self, insn: u16) -> String;
|
||||
}
|
||||
|
||||
pub mod disassembler;
|
||||
pub mod flags;
|
||||
pub mod instruction;
|
||||
pub mod mode;
|
||||
pub mod quirks;
|
||||
|
||||
use self::disassembler::{Dis, Insn};
|
||||
use self::{
|
||||
disassembler::{Dis, Disassembler, Insn},
|
||||
flags::Flags,
|
||||
mode::Mode,
|
||||
quirks::Quirks,
|
||||
};
|
||||
use crate::{
|
||||
bus::{Bus, Read, Region, Write},
|
||||
error::{Error, Result},
|
||||
@ -28,100 +31,6 @@ type Reg = usize;
|
||||
type Adr = u16;
|
||||
type Nib = u8;
|
||||
|
||||
/// Controls the authenticity behavior of the CPU on a granular level.
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct Quirks {
|
||||
/// Binary ops in `8xy`(`1`, `2`, `3`) shouldn't set vF to 0
|
||||
pub bin_ops: bool,
|
||||
/// Shift ops in `8xy`(`6`, `E`) shouldn't source from vY instead of vX
|
||||
pub shift: bool,
|
||||
/// Draw operations shouldn't pause execution until the next timer tick
|
||||
pub draw_wait: bool,
|
||||
/// DMA instructions `Fx55`/`Fx65` shouldn't change I to I + x + 1
|
||||
pub dma_inc: bool,
|
||||
/// Indexed jump instructions should go to `adr` + v`a` where `a` is high nibble of `adr`.
|
||||
pub stupid_jumps: bool,
|
||||
}
|
||||
|
||||
impl From<bool> for Quirks {
|
||||
fn from(value: bool) -> Self {
|
||||
if value {
|
||||
Quirks {
|
||||
bin_ops: true,
|
||||
shift: true,
|
||||
draw_wait: true,
|
||||
dma_inc: true,
|
||||
stupid_jumps: false,
|
||||
}
|
||||
} else {
|
||||
Quirks {
|
||||
bin_ops: false,
|
||||
shift: false,
|
||||
draw_wait: false,
|
||||
dma_inc: false,
|
||||
stupid_jumps: false,
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl Default for Quirks {
|
||||
fn default() -> Self {
|
||||
Self::from(false)
|
||||
}
|
||||
}
|
||||
|
||||
/// Represents flags that aid in operation, but aren't inherent to the CPU
|
||||
#[derive(Clone, Debug, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct ControlFlags {
|
||||
/// Set when debug (live disassembly) mode enabled
|
||||
pub debug: bool,
|
||||
/// Set when the emulator is paused by the user and should not update
|
||||
pub pause: bool,
|
||||
/// Set when the emulator is waiting for a keypress
|
||||
pub keypause: bool,
|
||||
/// Set when the emulator is waiting for a frame to be drawn
|
||||
pub draw_wait: bool,
|
||||
/// Set to the last key that's been *released* after a keypause
|
||||
pub lastkey: Option<usize>,
|
||||
/// Represents the set of emulator [Quirks] to enable
|
||||
pub quirks: Quirks,
|
||||
/// Represents the number of instructions to run per tick of the internal timer
|
||||
pub monotonic: Option<usize>,
|
||||
}
|
||||
|
||||
impl ControlFlags {
|
||||
/// Toggles debug mode
|
||||
///
|
||||
/// # Examples
|
||||
/// ```rust
|
||||
/// # use chirp::*;
|
||||
/// let mut cpu = CPU::default();
|
||||
/// assert_eq!(true, cpu.flags.debug);
|
||||
/// // Toggle debug mode
|
||||
/// cpu.flags.debug();
|
||||
/// assert_eq!(false, cpu.flags.debug);
|
||||
/// ```
|
||||
pub fn debug(&mut self) {
|
||||
self.debug = !self.debug
|
||||
}
|
||||
|
||||
/// Toggles pause
|
||||
///
|
||||
/// # Examples
|
||||
/// ```rust
|
||||
/// # use chirp::*;
|
||||
/// let mut cpu = CPU::default();
|
||||
/// assert_eq!(false, cpu.flags.pause);
|
||||
/// // Pause the cpu
|
||||
/// cpu.flags.pause();
|
||||
/// assert_eq!(true, cpu.flags.pause);
|
||||
/// ```
|
||||
pub fn pause(&mut self) {
|
||||
self.pause = !self.pause
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||
struct Timers {
|
||||
frame: Instant,
|
||||
@ -142,8 +51,8 @@ impl Default for Timers {
|
||||
#[derive(Clone, Debug, PartialEq)]
|
||||
pub struct CPU {
|
||||
/// Flags that control how the CPU behaves, but which aren't inherent to the
|
||||
/// implementation. Includes [Quirks], target IPF, etc.
|
||||
pub flags: ControlFlags,
|
||||
/// chip-8. Includes [Quirks], target IPF, etc.
|
||||
pub flags: Flags,
|
||||
// memory map info
|
||||
screen: Adr,
|
||||
font: Adr,
|
||||
@ -188,7 +97,7 @@ impl CPU {
|
||||
sp: Adr,
|
||||
disassembler: Dis,
|
||||
breakpoints: Vec<Adr>,
|
||||
flags: ControlFlags,
|
||||
flags: Flags,
|
||||
) -> Self {
|
||||
CPU {
|
||||
disassembler,
|
||||
@ -563,7 +472,7 @@ impl CPU {
|
||||
/// ```
|
||||
pub fn tick(&mut self, bus: &mut Bus) -> Result<&mut Self> {
|
||||
// Do nothing if paused
|
||||
if self.flags.pause || self.flags.draw_wait || self.flags.keypause {
|
||||
if self.flags.is_paused() {
|
||||
// always tick in test mode
|
||||
if self.flags.monotonic.is_some() {
|
||||
self.cycle += 1;
|
||||
@ -687,7 +596,7 @@ impl Default for CPU {
|
||||
sound: 0.0,
|
||||
cycle: 0,
|
||||
keys: [false; 16],
|
||||
flags: ControlFlags {
|
||||
flags: Flags {
|
||||
debug: true,
|
||||
..Default::default()
|
||||
},
|
||||
@ -697,471 +606,3 @@ impl Default for CPU {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl CPU {
|
||||
/// Executes a single [Insn]
|
||||
#[inline(always)]
|
||||
#[rustfmt::skip]
|
||||
fn execute(&mut self, bus: &mut Bus, instruction: Insn) {
|
||||
match instruction {
|
||||
Insn::cls => self.clear_screen(bus),
|
||||
Insn::ret => self.ret(bus),
|
||||
Insn::jmp { A } => self.jump(A),
|
||||
Insn::call { A } => self.call(A, bus),
|
||||
Insn::seb { B, x } => self.skip_equals_immediate(x, B),
|
||||
Insn::sneb { B, x } => self.skip_not_equals_immediate(x, B),
|
||||
Insn::se { y, x } => self.skip_equals(x, y),
|
||||
Insn::movb { B, x } => self.load_immediate(x, B),
|
||||
Insn::addb { B, x } => self.add_immediate(x, B),
|
||||
Insn::mov { x, y } => self.load(x, y),
|
||||
Insn::or { y, x } => self.or(x, y),
|
||||
Insn::and { y, x } => self.and(x, y),
|
||||
Insn::xor { y, x } => self.xor(x, y),
|
||||
Insn::add { y, x } => self.add(x, y),
|
||||
Insn::sub { y, x } => self.sub(x, y),
|
||||
Insn::shr { y, x } => self.shift_right(x, y),
|
||||
Insn::bsub { y, x } => self.backwards_sub(x, y),
|
||||
Insn::shl { y, x } => self.shift_left(x, y),
|
||||
Insn::sne { y, x } => self.skip_not_equals(x, y),
|
||||
Insn::movI { A } => self.load_i_immediate(A),
|
||||
Insn::jmpr { A } => self.jump_indexed(A),
|
||||
Insn::rand { B, x } => self.rand(x, B),
|
||||
Insn::draw { x, y, n } => self.draw(x, y, n, bus),
|
||||
Insn::sek { x } => self.skip_key_equals(x),
|
||||
Insn::snek { x } => self.skip_key_not_equals(x),
|
||||
Insn::getdt { x } => self.load_delay_timer(x),
|
||||
Insn::waitk { x } => self.wait_for_key(x),
|
||||
Insn::setdt { x } => self.store_delay_timer(x),
|
||||
Insn::movst { x } => self.store_sound_timer(x),
|
||||
Insn::addI { x } => self.add_i(x),
|
||||
Insn::font { x } => self.load_sprite(x),
|
||||
Insn::bcd { x } => self.bcd_convert(x, bus),
|
||||
Insn::dmao { x } => self.store_dma(x, bus),
|
||||
Insn::dmai { x } => self.load_dma(x, bus),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Below this point, comments may be duplicated per impl' block,
|
||||
// since some opcodes handle multiple instructions.
|
||||
|
||||
// |`0aaa`| Issues a "System call" (ML routine)
|
||||
//
|
||||
// |opcode| effect |
|
||||
// |------|------------------------------------|
|
||||
// |`00e0`| Clear screen memory to all 0 |
|
||||
// |`00ee`| Return from subroutine |
|
||||
impl CPU {
|
||||
/// |`00e0`| Clears the screen memory to 0
|
||||
#[inline(always)]
|
||||
fn clear_screen(&mut self, bus: &mut Bus) {
|
||||
if let Some(screen) = bus.get_region_mut(Region::Screen) {
|
||||
screen.fill(0);
|
||||
}
|
||||
}
|
||||
/// |`00ee`| Returns from subroutine
|
||||
#[inline(always)]
|
||||
fn ret(&mut self, bus: &impl Read<u16>) {
|
||||
self.sp = self.sp.wrapping_add(2);
|
||||
self.pc = bus.read(self.sp);
|
||||
}
|
||||
}
|
||||
|
||||
// |`1aaa`| Sets pc to an absolute address
|
||||
impl CPU {
|
||||
/// |`1aaa`| Sets the program counter to an absolute address
|
||||
#[inline(always)]
|
||||
fn jump(&mut self, a: Adr) {
|
||||
// jump to self == halt
|
||||
if a.wrapping_add(2) == self.pc {
|
||||
self.flags.pause = true;
|
||||
}
|
||||
self.pc = a;
|
||||
}
|
||||
}
|
||||
|
||||
// |`2aaa`| Pushes pc onto the stack, then jumps to a
|
||||
impl CPU {
|
||||
/// |`2aaa`| Pushes pc onto the stack, then jumps to a
|
||||
#[inline(always)]
|
||||
fn call(&mut self, a: Adr, bus: &mut impl Write<u16>) {
|
||||
bus.write(self.sp, self.pc);
|
||||
self.sp = self.sp.wrapping_sub(2);
|
||||
self.pc = a;
|
||||
}
|
||||
}
|
||||
|
||||
// |`3xbb`| Skips next instruction if register X == b
|
||||
impl CPU {
|
||||
/// |`3xbb`| Skips the next instruction if register X == b
|
||||
#[inline(always)]
|
||||
fn skip_equals_immediate(&mut self, x: Reg, b: u8) {
|
||||
if self.v[x] == b {
|
||||
self.pc = self.pc.wrapping_add(2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// |`4xbb`| Skips next instruction if register X != b
|
||||
impl CPU {
|
||||
/// |`4xbb`| Skips the next instruction if register X != b
|
||||
#[inline(always)]
|
||||
fn skip_not_equals_immediate(&mut self, x: Reg, b: u8) {
|
||||
if self.v[x] != b {
|
||||
self.pc = self.pc.wrapping_add(2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// |`5xyn`| Performs a register-register comparison
|
||||
//
|
||||
// |opcode| effect |
|
||||
// |------|------------------------------------|
|
||||
// |`5XY0`| Skip next instruction if vX == vY |
|
||||
impl CPU {
|
||||
/// |`5xy0`| Skips the next instruction if register X != register Y
|
||||
#[inline(always)]
|
||||
fn skip_equals(&mut self, x: Reg, y: Reg) {
|
||||
if self.v[x] == self.v[y] {
|
||||
self.pc = self.pc.wrapping_add(2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// |`6xbb`| Loads immediate byte b into register vX
|
||||
impl CPU {
|
||||
/// |`6xbb`| Loads immediate byte b into register vX
|
||||
#[inline(always)]
|
||||
fn load_immediate(&mut self, x: Reg, b: u8) {
|
||||
self.v[x] = b;
|
||||
}
|
||||
}
|
||||
|
||||
// |`7xbb`| Adds immediate byte b to register vX
|
||||
impl CPU {
|
||||
/// |`7xbb`| Adds immediate byte b to register vX
|
||||
#[inline(always)]
|
||||
fn add_immediate(&mut self, x: Reg, b: u8) {
|
||||
self.v[x] = self.v[x].wrapping_add(b);
|
||||
}
|
||||
}
|
||||
|
||||
// |`8xyn`| Performs ALU operation
|
||||
//
|
||||
// |opcode| effect |
|
||||
// |------|------------------------------------|
|
||||
// |`8xy0`| Y = X |
|
||||
// |`8xy1`| X = X | Y |
|
||||
// |`8xy2`| X = X & Y |
|
||||
// |`8xy3`| X = X ^ Y |
|
||||
// |`8xy4`| X = X + Y; Set vF=carry |
|
||||
// |`8xy5`| X = X - Y; Set vF=carry |
|
||||
// |`8xy6`| X = X >> 1 |
|
||||
// |`8xy7`| X = Y - X; Set vF=carry |
|
||||
// |`8xyE`| X = X << 1 |
|
||||
impl CPU {
|
||||
/// |`8xy0`| Loads the value of y into x
|
||||
#[inline(always)]
|
||||
fn load(&mut self, x: Reg, y: Reg) {
|
||||
self.v[x] = self.v[y];
|
||||
}
|
||||
/// |`8xy1`| Performs bitwise or of vX and vY, and stores the result in vX
|
||||
///
|
||||
/// # Quirk
|
||||
/// The original chip-8 interpreter will clobber vF for any 8-series instruction
|
||||
#[inline(always)]
|
||||
fn or(&mut self, x: Reg, y: Reg) {
|
||||
self.v[x] |= self.v[y];
|
||||
if !self.flags.quirks.bin_ops {
|
||||
self.v[0xf] = 0;
|
||||
}
|
||||
}
|
||||
/// |`8xy2`| Performs bitwise and of vX and vY, and stores the result in vX
|
||||
///
|
||||
/// # Quirk
|
||||
/// The original chip-8 interpreter will clobber vF for any 8-series instruction
|
||||
#[inline(always)]
|
||||
fn and(&mut self, x: Reg, y: Reg) {
|
||||
self.v[x] &= self.v[y];
|
||||
if !self.flags.quirks.bin_ops {
|
||||
self.v[0xf] = 0;
|
||||
}
|
||||
}
|
||||
/// |`8xy3`| Performs bitwise xor of vX and vY, and stores the result in vX
|
||||
///
|
||||
/// # Quirk
|
||||
/// The original chip-8 interpreter will clobber vF for any 8-series instruction
|
||||
#[inline(always)]
|
||||
fn xor(&mut self, x: Reg, y: Reg) {
|
||||
self.v[x] ^= self.v[y];
|
||||
if !self.flags.quirks.bin_ops {
|
||||
self.v[0xf] = 0;
|
||||
}
|
||||
}
|
||||
/// |`8xy4`| Performs addition of vX and vY, and stores the result in vX
|
||||
#[inline(always)]
|
||||
fn add(&mut self, x: Reg, y: Reg) {
|
||||
let carry;
|
||||
(self.v[x], carry) = self.v[x].overflowing_add(self.v[y]);
|
||||
self.v[0xf] = carry.into();
|
||||
}
|
||||
/// |`8xy5`| Performs subtraction of vX and vY, and stores the result in vX
|
||||
#[inline(always)]
|
||||
fn sub(&mut self, x: Reg, y: Reg) {
|
||||
let carry;
|
||||
(self.v[x], carry) = self.v[x].overflowing_sub(self.v[y]);
|
||||
self.v[0xf] = (!carry).into();
|
||||
}
|
||||
/// |`8xy6`| Performs bitwise right shift of vX
|
||||
///
|
||||
/// # Quirk
|
||||
/// On the original chip-8 interpreter, this shifts vY and stores the result in vX
|
||||
#[inline(always)]
|
||||
fn shift_right(&mut self, x: Reg, y: Reg) {
|
||||
let src: Reg = if self.flags.quirks.shift { x } else { y };
|
||||
let shift_out = self.v[src] & 1;
|
||||
self.v[x] = self.v[src] >> 1;
|
||||
self.v[0xf] = shift_out;
|
||||
}
|
||||
/// |`8xy7`| Performs subtraction of vY and vX, and stores the result in vX
|
||||
#[inline(always)]
|
||||
fn backwards_sub(&mut self, x: Reg, y: Reg) {
|
||||
let carry;
|
||||
(self.v[x], carry) = self.v[y].overflowing_sub(self.v[x]);
|
||||
self.v[0xf] = (!carry).into();
|
||||
}
|
||||
/// 8X_E: Performs bitwise left shift of vX
|
||||
///
|
||||
/// # Quirk
|
||||
/// On the original chip-8 interpreter, this would perform the operation on vY
|
||||
/// and store the result in vX. This behavior was left out, for now.
|
||||
#[inline(always)]
|
||||
fn shift_left(&mut self, x: Reg, y: Reg) {
|
||||
let src: Reg = if self.flags.quirks.shift { x } else { y };
|
||||
let shift_out: u8 = self.v[src] >> 7;
|
||||
self.v[x] = self.v[src] << 1;
|
||||
self.v[0xf] = shift_out;
|
||||
}
|
||||
}
|
||||
|
||||
// |`9xyn`| Performs a register-register comparison
|
||||
//
|
||||
// |opcode| effect |
|
||||
// |------|------------------------------------|
|
||||
// |`9XY0`| Skip next instruction if vX != vY |
|
||||
impl CPU {
|
||||
/// |`9xy0`| Skip next instruction if X != y
|
||||
#[inline(always)]
|
||||
fn skip_not_equals(&mut self, x: Reg, y: Reg) {
|
||||
if self.v[x] != self.v[y] {
|
||||
self.pc = self.pc.wrapping_add(2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// |`Aaaa`| Load address #a into register I
|
||||
impl CPU {
|
||||
/// |`Aadr`| Load address #adr into register I
|
||||
#[inline(always)]
|
||||
fn load_i_immediate(&mut self, a: Adr) {
|
||||
self.i = a;
|
||||
}
|
||||
}
|
||||
|
||||
// |`Baaa`| Jump to &adr + v0
|
||||
impl CPU {
|
||||
/// |`Badr`| Jump to &adr + v0
|
||||
///
|
||||
/// Quirk:
|
||||
/// On the Super-Chip, this does stupid shit
|
||||
#[inline(always)]
|
||||
fn jump_indexed(&mut self, a: Adr) {
|
||||
let reg = if self.flags.quirks.stupid_jumps {
|
||||
a as usize >> 8
|
||||
} else {
|
||||
0
|
||||
};
|
||||
self.pc = a.wrapping_add(self.v[reg] as Adr);
|
||||
}
|
||||
}
|
||||
|
||||
// |`Cxbb`| Stores a random number & the provided byte into vX
|
||||
impl CPU {
|
||||
/// |`Cxbb`| Stores a random number & the provided byte into vX
|
||||
#[inline(always)]
|
||||
fn rand(&mut self, x: Reg, b: u8) {
|
||||
self.v[x] = random::<u8>() & b;
|
||||
}
|
||||
}
|
||||
|
||||
// |`Dxyn`| Draws n-byte sprite to the screen at coordinates (vX, vY)
|
||||
impl CPU {
|
||||
/// |`Dxyn`| Draws n-byte sprite to the screen at coordinates (vX, vY)
|
||||
///
|
||||
/// # Quirk
|
||||
/// On the original chip-8 interpreter, this will wait for a VBI
|
||||
#[inline(always)]
|
||||
fn draw(&mut self, x: Reg, y: Reg, n: Nib, bus: &mut Bus) {
|
||||
let (x, y) = (self.v[x] as u16 % 64, self.v[y] as u16 % 32);
|
||||
if !self.flags.quirks.draw_wait {
|
||||
self.flags.draw_wait = true;
|
||||
}
|
||||
self.v[0xf] = 0;
|
||||
for byte in 0..n as u16 {
|
||||
if y + byte > 32 {
|
||||
return;
|
||||
}
|
||||
// Calculate the lower bound address based on the X,Y position on the screen
|
||||
let addr = (y + byte) * 8 + (x & 0x3f) / 8 + self.screen;
|
||||
// Read a byte of sprite data into a u16, and shift it x % 8 bits
|
||||
let sprite: u8 = bus.read(self.i + byte);
|
||||
let sprite =
|
||||
(sprite as u16) << (8 - (x & 7)) & if x % 64 > 56 { 0xff00 } else { 0xffff };
|
||||
// Read a u16 from the bus containing the two bytes which might need to be updated
|
||||
let mut screen: u16 = bus.read(addr);
|
||||
// Save the bits-toggled-off flag if necessary
|
||||
if screen & sprite != 0 {
|
||||
self.v[0xF] = 1
|
||||
}
|
||||
// Update the screen word by XORing the sprite byte
|
||||
screen ^= sprite;
|
||||
// Save the result to the screen
|
||||
bus.write(addr, screen);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// |`Exbb`| Skips instruction on value of keypress
|
||||
//
|
||||
// |opcode| effect |
|
||||
// |------|------------------------------------|
|
||||
// |`eX9e`| Skip next instruction if key == vX |
|
||||
// |`eXa1`| Skip next instruction if key != vX |
|
||||
impl CPU {
|
||||
/// |`Ex9E`| Skip next instruction if key == vX
|
||||
#[inline(always)]
|
||||
fn skip_key_equals(&mut self, x: Reg) {
|
||||
let x = self.v[x] as usize;
|
||||
if self.keys[x] {
|
||||
self.pc += 2;
|
||||
}
|
||||
}
|
||||
/// |`ExaE`| Skip next instruction if key != vX
|
||||
#[inline(always)]
|
||||
fn skip_key_not_equals(&mut self, x: Reg) {
|
||||
let x = self.v[x] as usize;
|
||||
if !self.keys[x] {
|
||||
self.pc += 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// |`Fxbb`| Performs IO
|
||||
//
|
||||
// |opcode| effect |
|
||||
// |------|------------------------------------|
|
||||
// |`fX07`| Set vX to value in delay timer |
|
||||
// |`fX0a`| Wait for input, store key in vX |
|
||||
// |`fX15`| Set sound timer to the value in vX |
|
||||
// |`fX18`| set delay timer to the value in vX |
|
||||
// |`fX1e`| Add vX to I |
|
||||
// |`fX29`| Load sprite for character x into I |
|
||||
// |`fX33`| BCD convert X into I[0..3] |
|
||||
// |`fX55`| DMA Stor from I to registers 0..=X |
|
||||
// |`fX65`| DMA Load from I to registers 0..=X |
|
||||
impl CPU {
|
||||
/// |`Fx07`| Get the current DT, and put it in vX
|
||||
/// ```py
|
||||
/// vX = DT
|
||||
/// ```
|
||||
#[inline(always)]
|
||||
fn load_delay_timer(&mut self, x: Reg) {
|
||||
self.v[x] = self.delay as u8;
|
||||
}
|
||||
/// |`Fx0A`| Wait for key, then vX = K
|
||||
#[inline(always)]
|
||||
fn wait_for_key(&mut self, x: Reg) {
|
||||
if let Some(key) = self.flags.lastkey {
|
||||
self.v[x] = key as u8;
|
||||
self.flags.lastkey = None;
|
||||
} else {
|
||||
self.pc = self.pc.wrapping_sub(2);
|
||||
self.flags.keypause = true;
|
||||
}
|
||||
}
|
||||
/// |`Fx15`| Load vX into DT
|
||||
/// ```py
|
||||
/// DT = vX
|
||||
/// ```
|
||||
#[inline(always)]
|
||||
fn store_delay_timer(&mut self, x: Reg) {
|
||||
self.delay = self.v[x] as f64;
|
||||
}
|
||||
/// |`Fx18`| Load vX into ST
|
||||
/// ```py
|
||||
/// ST = vX;
|
||||
/// ```
|
||||
#[inline(always)]
|
||||
fn store_sound_timer(&mut self, x: Reg) {
|
||||
self.sound = self.v[x] as f64;
|
||||
}
|
||||
/// |`Fx1e`| Add vX to I,
|
||||
/// ```py
|
||||
/// I += vX;
|
||||
/// ```
|
||||
#[inline(always)]
|
||||
fn add_i(&mut self, x: Reg) {
|
||||
self.i += self.v[x] as u16;
|
||||
}
|
||||
/// |`Fx29`| Load sprite for character x into I
|
||||
/// ```py
|
||||
/// I = sprite(X);
|
||||
/// ```
|
||||
#[inline(always)]
|
||||
fn load_sprite(&mut self, x: Reg) {
|
||||
self.i = self.font + (5 * (self.v[x] as Adr % 0x10));
|
||||
}
|
||||
/// |`Fx33`| BCD convert X into I`[0..3]`
|
||||
#[inline(always)]
|
||||
fn bcd_convert(&mut self, x: Reg, bus: &mut Bus) {
|
||||
let x = self.v[x];
|
||||
bus.write(self.i.wrapping_add(2), x % 10);
|
||||
bus.write(self.i.wrapping_add(1), x / 10 % 10);
|
||||
bus.write(self.i, x / 100 % 10);
|
||||
}
|
||||
/// |`Fx55`| DMA Stor from I to registers 0..=X
|
||||
///
|
||||
/// # Quirk
|
||||
/// The original chip-8 interpreter uses I to directly index memory,
|
||||
/// with the side effect of leaving I as I+X+1 after the transfer is done.
|
||||
#[inline(always)]
|
||||
fn store_dma(&mut self, x: Reg, bus: &mut Bus) {
|
||||
let i = self.i as usize;
|
||||
for (reg, value) in bus
|
||||
.get_mut(i..=i + x)
|
||||
.unwrap_or_default()
|
||||
.iter_mut()
|
||||
.enumerate()
|
||||
{
|
||||
*value = self.v[reg]
|
||||
}
|
||||
if !self.flags.quirks.dma_inc {
|
||||
self.i += x as Adr + 1;
|
||||
}
|
||||
}
|
||||
/// |`Fx65`| DMA Load from I to registers 0..=X
|
||||
///
|
||||
/// # Quirk
|
||||
/// The original chip-8 interpreter uses I to directly index memory,
|
||||
/// with the side effect of leaving I as I+X+1 after the transfer is done.
|
||||
#[inline(always)]
|
||||
fn load_dma(&mut self, x: Reg, bus: &mut Bus) {
|
||||
let i = self.i as usize;
|
||||
for (reg, value) in bus.get(i..=i + x).unwrap_or_default().iter().enumerate() {
|
||||
self.v[reg] = *value;
|
||||
}
|
||||
if !self.flags.quirks.dma_inc {
|
||||
self.i += x as Adr + 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,14 +1,20 @@
|
||||
//! A disassembler for Chip-8 opcodes
|
||||
#![allow(clippy::bad_bit_mask)]
|
||||
use super::Disassembler;
|
||||
use imperative_rs::InstructionSet;
|
||||
use owo_colors::{OwoColorize, Style};
|
||||
use std::fmt::Display;
|
||||
|
||||
/// Disassembles Chip-8 instructions
|
||||
pub trait Disassembler {
|
||||
/// Disassemble a single instruction
|
||||
fn once(&self, insn: u16) -> String;
|
||||
}
|
||||
|
||||
#[allow(non_camel_case_types, non_snake_case, missing_docs)]
|
||||
#[derive(Clone, Copy, Debug, InstructionSet, PartialEq, Eq)]
|
||||
/// Implements a Disassembler using imperative_rs
|
||||
pub enum Insn {
|
||||
// Base instruction set
|
||||
/// | 00e0 | Clear screen memory to 0s
|
||||
#[opcode = "0x00e0"]
|
||||
cls,
|
||||
@ -77,7 +83,7 @@ pub enum Insn {
|
||||
rand { B: u8, x: usize },
|
||||
/// | Dxyn | Draws n-byte sprite to the screen at coordinates (vX, vY)
|
||||
#[opcode = "0xdxyn"]
|
||||
draw { x: usize, y: usize, n: u8 },
|
||||
draw { y: usize, x: usize, n: u8 },
|
||||
/// | eX9e | Skip next instruction if key == vX
|
||||
#[opcode = "0xex9e"]
|
||||
sek { x: usize },
|
||||
@ -111,19 +117,49 @@ pub enum Insn {
|
||||
// | fX65 | DMA Load from I to registers 0..X
|
||||
#[opcode = "0xfx65"]
|
||||
dmai { x: usize },
|
||||
|
||||
// Super Chip extensions
|
||||
/// | 00cN | Scroll the screen down
|
||||
#[opcode = "0x00cn"]
|
||||
scd { n: u8 },
|
||||
/// | 00fb | Scroll the screen right
|
||||
#[opcode = "0x00fb"]
|
||||
scr,
|
||||
/// | 00fc | Scroll the screen left
|
||||
#[opcode = "0x00fc"]
|
||||
scl,
|
||||
/// | 00fd | Exit (halt and catch fire)
|
||||
#[opcode = "0x00fd"]
|
||||
halt,
|
||||
/// | 00fe | Return to low-resolution mode
|
||||
#[opcode = "0x00fe"]
|
||||
lores,
|
||||
/// | 00ff | Enter high-resolution mode
|
||||
#[opcode = "0x00ff"]
|
||||
hires,
|
||||
/// | fx30 | Enter high-resolution mode
|
||||
#[opcode = "0xfx30"]
|
||||
hfont { x: usize },
|
||||
/// | fx75 | Save to "flag registers"
|
||||
#[opcode = "0xfx75"]
|
||||
flgo { x: usize },
|
||||
/// | fx85 | Load from "flag registers"
|
||||
#[opcode = "0xfx85"]
|
||||
flgi { x: usize },
|
||||
}
|
||||
|
||||
impl Display for Insn {
|
||||
#[rustfmt::skip]
|
||||
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
|
||||
match self {
|
||||
// Base instruction set
|
||||
Insn::cls => write!(f, "cls "),
|
||||
Insn::ret => write!(f, "ret "),
|
||||
Insn::jmp { A } => write!(f, "jmp {A:03x}"),
|
||||
Insn::call { A } => write!(f, "call {A:03x}"),
|
||||
Insn::seb { B, x } => write!(f, "se #{B:02x}, v{x:X}"),
|
||||
Insn::sneb { B, x } => write!(f, "sne #{B:02x}, v{x:X}"),
|
||||
Insn::se { y, x } => write!(f, "se v{x:X}, v{y:X}"),
|
||||
Insn::se { y, x } => write!(f, "se v{y:X}, v{x:X}"),
|
||||
Insn::movb { B, x } => write!(f, "mov #{B:02x}, v{x:X}"),
|
||||
Insn::addb { B, x } => write!(f, "add #{B:02x}, v{x:X}"),
|
||||
Insn::mov { x, y } => write!(f, "mov v{y:X}, v{x:X}"),
|
||||
@ -135,11 +171,11 @@ impl Display for Insn {
|
||||
Insn::shr { y, x } => write!(f, "shr v{y:X}, v{x:X}"),
|
||||
Insn::bsub { y, x } => write!(f, "bsub v{y:X}, v{x:X}"),
|
||||
Insn::shl { y, x } => write!(f, "shl v{y:X}, v{x:X}"),
|
||||
Insn::sne { y, x } => write!(f, "sne v{x:X}, v{y:X}"),
|
||||
Insn::sne { y, x } => write!(f, "sne v{y:X}, v{x:X}"),
|
||||
Insn::movI { A } => write!(f, "mov ${A:03x}, I"),
|
||||
Insn::jmpr { A } => write!(f, "jmp ${A:03x}+v0"),
|
||||
Insn::rand { B, x } => write!(f, "rand #{B:02x}, v{x:X}"),
|
||||
Insn::draw { x, y, n } => write!(f, "draw #{n:x}, v{x:X}, v{y:X}"),
|
||||
Insn::draw { y, x, n } => write!(f, "draw #{n:x}, v{x:X}, v{y:X}"),
|
||||
Insn::sek { x } => write!(f, "sek v{x:X}"),
|
||||
Insn::snek { x } => write!(f, "snek v{x:X}"),
|
||||
Insn::getdt { x } => write!(f, "mov DT, v{x:X}"),
|
||||
@ -151,6 +187,16 @@ impl Display for Insn {
|
||||
Insn::bcd { x } => write!(f, "bcd v{x:X}, &I"),
|
||||
Insn::dmao { x } => write!(f, "dmao v{x:X}"),
|
||||
Insn::dmai { x } => write!(f, "dmai v{x:X}"),
|
||||
// Super Chip extensions
|
||||
Insn::scd { n } => write!(f, "scd #{n:x}"),
|
||||
Insn::scr => write!(f, "scr "),
|
||||
Insn::scl => write!(f, "scl "),
|
||||
Insn::halt => write!(f, "halt "),
|
||||
Insn::lores => write!(f, "lores "),
|
||||
Insn::hires => write!(f, "hires "),
|
||||
Insn::hfont { x } => write!(f, "hfont v{x:X}"),
|
||||
Insn::flgo { x } => write!(f, "flgo v{x:X}"),
|
||||
Insn::flgi { x } => write!(f, "flgi v{x:X}"),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
63
src/cpu/flags.rs
Normal file
63
src/cpu/flags.rs
Normal file
@ -0,0 +1,63 @@
|
||||
//! Represents [Flags] that aid in implementation but aren't a part of the Chip-8 spec
|
||||
|
||||
use super::{Mode, Quirks};
|
||||
|
||||
/// Represents flags that aid in implementation but aren't a part of the Chip-8 spec
|
||||
#[derive(Clone, Debug, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct Flags {
|
||||
/// Set when debug (live disassembly) mode enabled
|
||||
pub debug: bool,
|
||||
/// Set when the emulator is paused by the user and should not update
|
||||
pub pause: bool,
|
||||
/// Set when the emulator is waiting for a keypress
|
||||
pub keypause: bool,
|
||||
/// Set when the emulator is waiting for a frame to be drawn
|
||||
pub draw_wait: bool,
|
||||
/// Set when the emulator is in high-res mode
|
||||
pub draw_mode: bool,
|
||||
/// Set to the last key that's been *released* after a keypause
|
||||
pub lastkey: Option<usize>,
|
||||
/// Represents the current emulator [Mode]
|
||||
pub mode: Mode,
|
||||
/// Represents the set of emulator [Quirks] to enable, independent of the [Mode]
|
||||
pub quirks: Quirks,
|
||||
/// Represents the number of instructions to run per tick of the internal timer
|
||||
pub monotonic: Option<usize>,
|
||||
}
|
||||
|
||||
impl Flags {
|
||||
/// Toggles debug mode
|
||||
///
|
||||
/// # Examples
|
||||
/// ```rust
|
||||
/// # use chirp::*;
|
||||
/// let mut cpu = CPU::default();
|
||||
/// assert_eq!(true, cpu.flags.debug);
|
||||
/// // Toggle debug mode
|
||||
/// cpu.flags.debug();
|
||||
/// assert_eq!(false, cpu.flags.debug);
|
||||
/// ```
|
||||
pub fn debug(&mut self) {
|
||||
self.debug = !self.debug
|
||||
}
|
||||
|
||||
/// Toggles pause
|
||||
///
|
||||
/// # Examples
|
||||
/// ```rust
|
||||
/// # use chirp::*;
|
||||
/// let mut cpu = CPU::default();
|
||||
/// assert_eq!(false, cpu.flags.pause);
|
||||
/// // Pause the cpu
|
||||
/// cpu.flags.pause();
|
||||
/// assert_eq!(true, cpu.flags.pause);
|
||||
/// ```
|
||||
pub fn pause(&mut self) {
|
||||
self.pause = !self.pause
|
||||
}
|
||||
|
||||
/// Gets whether the CPU is paused for any reason
|
||||
pub fn is_paused(&self) -> bool {
|
||||
self.pause || self.draw_wait || self.keypause
|
||||
}
|
||||