26 Commits

Author SHA1 Message Date
57c2ac681c cpu: fix renaming mistake "screen" -> "mem" 2023-04-29 18:34:24 -05:00
ea357be477 Monotonic: This flag is being deprecated soon, switch it for bool 2023-04-29 18:20:49 -05:00
7d5718f384 cpu.rs: Separate lastkey from flags 2023-04-29 12:08:26 -05:00
c1219e60f0 cpu.rs: Refactor for modularity
- Break into submodules
  - Move bus into submodule of CPU
  - Keep program and charset rom inside CPU
  - Take only the screen on the external Bus
  - Refactor the disassembler into an instruction definition and the actual "Dis" item
2023-04-23 12:10:02 -05:00
92dc899510 Update copyright notices 2023-04-23 11:58:57 -05:00
45adf0a2b8 cpu.rs: Remove stack from main memory 2023-04-17 06:34:48 -05:00
95d4751cdd bus: Major refactor: auto-impl implicit casting for all numerics 2023-04-17 05:12:37 -05:00
7d25a9f5f1 quirks.rs: Prepare screen_wrap quirk for future xochip compat 2023-04-17 05:09:16 -05:00
674af62465 cpu.rs: Break into submodules 2023-04-14 21:25:41 -05:00
03a6934a59 tests.rs: BC_test tests flawed behavior. 2023-04-02 14:47:33 -05:00
83cc35c968 Move submodules to project root 2023-04-02 14:45:32 -05:00
89f66c3d5b Add chip8Archive as a submodule, for testing 2023-04-02 14:21:43 -05:00
f27537b3b8 tests: Update tests to match current behavior. 2023-04-01 02:31:51 -05:00
bb8015f33c Quirks: Make the Cosmac VIP behavior default. 2023-04-01 00:15:40 -05:00
7173b9e39b Break io into chirp-minifb, and refactor to use Results in more places 2023-04-01 00:14:15 -05:00
a676280ec8 clippy: Fix all clippy lints 2023-03-31 14:32:01 -05:00
cc3bc3a7fe Major Refactor: Make invalid states unrepresentable™️
- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
  - Now >10x faster
  - Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
  - (use option -S to set the number of instructions per epoch)
2023-03-30 08:27:06 -05:00
ce0dc954d0 tests: Improve cpu.rs line coverage to >99% 2023-03-28 12:31:56 -05:00
fbc0a0b2ea tests: Coverage and cleanup/speedup
- Improved test coverage to >80% of lines, functions
  - When doctests are included.
  - Wrote new unit tests:
    - Explicit tests for invalid instructions in the
      ranges {`5xyn`, `8xyn`, `9xyn`, `Fxbb`}
    - `rand` Tests for 1052671 cycles, to ensure
      randomly generated number is < ANDed byte
    - `Ex9E` (sek), `ExA1`(snek) will press only the expected key,
      then every key except the expected key, for every address
    - `Fx0A` (waitk) asserts based on the waveform of a keypress.
      After all, an A press is an A press.
- Improved test performance by printing slightly less
- Removed nightly requirement
  - (now optional, with feature = "unstable")
- Amended justfile to test with `cargo nextest` (nice)
- Changed release builds to optlevel 3
2023-03-28 07:33:17 -05:00
d5cfdc6802 tests: Move chip8-test-suite to integration tests. 2023-03-27 21:01:33 -05:00
b8720142c7 disassemble.rs: Make asm format more consistent. 2023-03-27 18:31:18 -05:00
0e91b103ed LICENSE: Add MIT Licence 2023-03-27 18:30:31 -05:00
784845b6f5 cpu.rs: Make quirks individually configurable 2023-03-27 17:27:55 -05:00
4b5de191d8 cpu/tests.rs: Use instruction function directly in non-parser tests 2023-03-26 19:04:36 -05:00
185712aeb6 cpu/tests.rs: Modularize and add new tests 2023-03-26 18:33:12 -05:00
73a69f3469 cpu.rs: Create unit tests for most instructions 2023-03-25 18:17:09 -05:00