Commit Graph

30 Commits

Author SHA1 Message Date
8bb34f2593 schip: Improve architecture & compatibility somewhat 2023-04-03 05:46:33 -05:00
acc7629516 schip: Add preliminary SuperChip support (no test) 2023-04-03 02:01:25 -05:00
03a6934a59 tests.rs: BC_test tests flawed behavior. 2023-04-02 14:47:33 -05:00
83cc35c968 Move submodules to project root 2023-04-02 14:45:32 -05:00
89f66c3d5b Add chip8Archive as a submodule, for testing 2023-04-02 14:21:43 -05:00
f27537b3b8 tests: Update tests to match current behavior. 2023-04-01 02:31:51 -05:00
bb8015f33c Quirks: Make the Cosmac VIP behavior default. 2023-04-01 00:15:40 -05:00
7173b9e39b Break io into chirp-minifb, and refactor to use Results in more places 2023-04-01 00:14:15 -05:00
a676280ec8 clippy: Fix all clippy lints 2023-03-31 14:32:01 -05:00
c1f457814d disassembler: 100% line coverage 2023-03-30 08:53:10 -05:00
cc3bc3a7fe Major Refactor: Make invalid states unrepresentable™️
- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
  - Now >10x faster
  - Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
  - (use option -S to set the number of instructions per epoch)
2023-03-30 08:27:06 -05:00
f60a4b3cc2 Refactor disassembler to use imperative-rs
It's like MAGIC. Easily cut out 200 LOC
2023-03-30 02:12:03 -05:00
e54f66f6c4 disassemble.rs: Update function names to match cpu.rs 2023-03-29 23:46:57 -05:00
b9c35c0e68 lib.rs: Deny (missing docs) 2023-03-29 23:45:39 -05:00
ce0dc954d0 tests: Improve cpu.rs line coverage to >99% 2023-03-28 12:31:56 -05:00
83c178413d tests: Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience. 2023-03-28 08:57:24 -05:00
fbc0a0b2ea tests: Coverage and cleanup/speedup
- Improved test coverage to >80% of lines, functions
  - When doctests are included.
  - Wrote new unit tests:
    - Explicit tests for invalid instructions in the
      ranges {`5xyn`, `8xyn`, `9xyn`, `Fxbb`}
    - `rand` Tests for 1052671 cycles, to ensure
      randomly generated number is < ANDed byte
    - `Ex9E` (sek), `ExA1`(snek) will press only the expected key,
      then every key except the expected key, for every address
    - `Fx0A` (waitk) asserts based on the waveform of a keypress.
      After all, an A press is an A press.
- Improved test performance by printing slightly less
- Removed nightly requirement
  - (now optional, with feature = "unstable")
- Amended justfile to test with `cargo nextest` (nice)
- Changed release builds to optlevel 3
2023-03-28 07:33:17 -05:00
d5cfdc6802 tests: Move chip8-test-suite to integration tests. 2023-03-27 21:01:33 -05:00
b8720142c7 disassemble.rs: Make asm format more consistent. 2023-03-27 18:31:18 -05:00
0e91b103ed LICENSE: Add MIT Licence 2023-03-27 18:30:31 -05:00
784845b6f5 cpu.rs: Make quirks individually configurable 2023-03-27 17:27:55 -05:00
a40ee94499 cpu/tests: Add chip8-test-suite, organize tests 2023-03-27 17:21:23 -05:00
4b5de191d8 cpu/tests.rs: Use instruction function directly in non-parser tests 2023-03-26 19:04:36 -05:00
185712aeb6 cpu/tests.rs: Modularize and add new tests 2023-03-26 18:33:12 -05:00
edd2b60665 cpu.rs: Refactor dump(&self) to do fewer allocations 2023-03-25 18:32:45 -05:00
73a69f3469 cpu.rs: Create unit tests for most instructions 2023-03-25 18:17:09 -05:00
c7447a26a3 disassemble.rs: Format with rustfmt 2023-03-25 17:37:09 -05:00
dc61bd0087 I/O: KISS the bus, attach a screen, plug in a controller
Chip-8 has no ROM, nor memory management.
- It's much easier to just use contiguous memory.
- Then we can return references to slices of that memory
- ~3x speed increase
Screen exists now, uses 24-bit framebuffer
- We have a 1-bit framebuffer
- I chose colors that look good to me
Controller exists as well, has 16 buttons
- Mapped "0 123 456 789 ab cdef" to (QWERTY) "X 123 QWE ASD zC 4RFV"
- Other chip-8 interpreters may use a different layout
  - This is good enough for now.
- F1-F9 map to control functions
  - F1, F2: Dump CPU registers/screen contents
  - F3, F4: Toggle disassembly/pause
  - F5:     Single-step the CPU, pausing after
  - F6, F7: Set/Unset breakpoint
  - F8, F9: Soft/Hard Reset CPU
2023-03-22 15:03:53 -05:00
2ba807d7a8 Rumpulator: Change name to Chumpulator 2023-03-10 15:33:36 -06:00
a721a00232 Initial commit:
Created outline of emulator:
The emulator has a Bus, which attaches a CPU to some Memory (Mapped Devices)
The design isn't particularly efficient, but the interpreter only needs to
run at ~500Hz or so. It's Rust. It can do that.

Instructions yet to be implemented:
Cxbb: "Store a random number, masked by bitmask bb, into vX"
Dxyn: "Draw an 8 by n sprite to the screen at coordinates (x, y)"
Fx0A: "Wait for a key, then set vX to the value of the pressed key"
Fx33: "BCD convert X, storing the results in &I[0..3]"

Thoughts going forward:
  - It's probably a good idea to parse instructions out into an enum.
    I had this in an earlier design, but it didn't really look that good.
    However, I haven't read many other emulators before, so I don't know the
    style people generally go for.
  - I haven't used a native graphics library before, and my cg class was done
    entirely in a web browser. That kinda sucks, honestly. Sure the skill
    might transfer well, but, >JS
2023-03-08 06:07:33 -06:00