Commit Graph

16 Commits

Author SHA1 Message Date
ea357be477 Monotonic: This flag is being deprecated soon, switch it for bool 2023-04-29 18:20:49 -05:00
7d5718f384 cpu.rs: Separate lastkey from flags 2023-04-29 12:08:26 -05:00
c1219e60f0 cpu.rs: Refactor for modularity
- Break into submodules
  - Move bus into submodule of CPU
  - Keep program and charset rom inside CPU
  - Take only the screen on the external Bus
  - Refactor the disassembler into an instruction definition and the actual "Dis" item
2023-04-23 12:10:02 -05:00
92dc899510 Update copyright notices 2023-04-23 11:58:57 -05:00
45adf0a2b8 cpu.rs: Remove stack from main memory 2023-04-17 06:34:48 -05:00
7d25a9f5f1 quirks.rs: Prepare screen_wrap quirk for future xochip compat 2023-04-17 05:09:16 -05:00
674af62465 cpu.rs: Break into submodules 2023-04-14 21:25:41 -05:00
946a6031fb tests: Update test to match new expected behavior 2023-04-03 05:47:42 -05:00
acc7629516 schip: Add preliminary SuperChip support (no test) 2023-04-03 02:01:25 -05:00
a4c548d0ec lib.rs: Remove crate::prelude, re-export in lib.rs 2023-04-01 02:31:06 -05:00
7173b9e39b Break io into chirp-minifb, and refactor to use Results in more places 2023-04-01 00:14:15 -05:00
a676280ec8 clippy: Fix all clippy lints 2023-03-31 14:32:01 -05:00
c1f457814d disassembler: 100% line coverage 2023-03-30 08:53:10 -05:00
cc3bc3a7fe Major Refactor: Make invalid states unrepresentable™️
- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
  - Now >10x faster
  - Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
  - (use option -S to set the number of instructions per epoch)
2023-03-30 08:27:06 -05:00
c194a3c53a Error: Remove FunkyMathError and Stringly Typed context 2023-03-29 23:42:41 -05:00
ce0dc954d0 tests: Improve cpu.rs line coverage to >99% 2023-03-28 12:31:56 -05:00