Commit Graph

12 Commits

Author SHA1 Message Date
5159afa3fd cpu.rs: Reference chaining mutable functions 2023-03-25 18:09:41 -05:00
49a6fc0377 dump.rs: Does not spark joy (remove dump.rs) 2023-03-25 17:45:22 -05:00
4ab7dcbe6a main.rs: General cleanup in preparation for refactor 2023-03-25 17:42:06 -05:00
f3badf41e8 io.rs: QOL fixups; Reuse WindowBuilder, #[derive(...)] FrameBufferFormat 2023-03-25 17:39:03 -05:00
c7447a26a3 disassemble.rs: Format with rustfmt 2023-03-25 17:37:09 -05:00
712acc5984 bus.rs: Improve region encoding with enums 2023-03-25 17:20:20 -05:00
e534041d00 gitignore: Add screen_dump.bin 2023-03-25 16:58:05 -05:00
dc61bd0087 I/O: KISS the bus, attach a screen, plug in a controller
Chip-8 has no ROM, nor memory management.
- It's much easier to just use contiguous memory.
- Then we can return references to slices of that memory
- ~3x speed increase
Screen exists now, uses 24-bit framebuffer
- We have a 1-bit framebuffer
- I chose colors that look good to me
Controller exists as well, has 16 buttons
- Mapped "0 123 456 789 ab cdef" to (QWERTY) "X 123 QWE ASD zC 4RFV"
- Other chip-8 interpreters may use a different layout
  - This is good enough for now.
- F1-F9 map to control functions
  - F1, F2: Dump CPU registers/screen contents
  - F3, F4: Toggle disassembly/pause
  - F5:     Single-step the CPU, pausing after
  - F6, F7: Set/Unset breakpoint
  - F8, F9: Soft/Hard Reset CPU
2023-03-22 15:03:53 -05:00
ef3d765651 experimentation: benchmarking and alternate impl's
- Do some basic benchmarking with std::time
- Try writing bus writer based on iterator
  - Fail, because that requires mutable iterator
  - Begin rewriting bus based on simpler design instead.
    - Simpler design uses a unified memory model,
      which grows based on the maximum addresses expected in it
    - Still uses the "infallible" Read/Write traits from previous
      implementation. :( Alas, it's much faster during operation,
      even if it takes longer to instantiate.
    - Reassessed the syntax for bus macro
  - Made CPU tick generic over bus::Read and bus::Write traits
2023-03-17 20:06:31 -05:00
2ba807d7a8 Rumpulator: Change name to Chumpulator 2023-03-10 15:33:36 -06:00
f03d03bf4e readme.md: Add readme.md 2023-03-10 15:33:02 -06:00
a721a00232 Initial commit:
Created outline of emulator:
The emulator has a Bus, which attaches a CPU to some Memory (Mapped Devices)
The design isn't particularly efficient, but the interpreter only needs to
run at ~500Hz or so. It's Rust. It can do that.

Instructions yet to be implemented:
Cxbb: "Store a random number, masked by bitmask bb, into vX"
Dxyn: "Draw an 8 by n sprite to the screen at coordinates (x, y)"
Fx0A: "Wait for a key, then set vX to the value of the pressed key"
Fx33: "BCD convert X, storing the results in &I[0..3]"

Thoughts going forward:
  - It's probably a good idea to parse instructions out into an enum.
    I had this in an earlier design, but it didn't really look that good.
    However, I haven't read many other emulators before, so I don't know the
    style people generally go for.
  - I haven't used a native graphics library before, and my cg class was done
    entirely in a web browser. That kinda sucks, honestly. Sure the skill
    might transfer well, but, >JS
2023-03-08 06:07:33 -06:00