Quirks: Make the Cosmac VIP behavior default.
This commit is contained in:
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bb8015f33c
@ -117,10 +117,10 @@ impl State {
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options.breakpoints,
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ControlFlags {
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quirks: chirp::cpu::Quirks {
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bin_ops: !options.vfreset,
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shift: !options.shift,
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draw_wait: !options.drawsync,
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dma_inc: !options.memory,
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bin_ops: options.vfreset,
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shift: options.shift,
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draw_wait: options.drawsync,
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dma_inc: options.memory,
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stupid_jumps: options.jumping,
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},
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debug: options.debug,
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259
src/cpu.rs
259
src/cpu.rs
@ -29,17 +29,17 @@ type Adr = u16;
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type Nib = u8;
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/// Controls the authenticity behavior of the CPU on a granular level.
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#[derive(Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct Quirks {
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/// Binary ops in `8xy`(`1`, `2`, `3`) should set vF to 0
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/// Binary ops in `8xy`(`1`, `2`, `3`) shouldn't set vF to 0
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pub bin_ops: bool,
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/// Shift ops in `8xy`(`6`, `E`) should source from vY instead of vX
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/// Shift ops in `8xy`(`6`, `E`) shouldn't source from vY instead of vX
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pub shift: bool,
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/// Draw operations should pause execution until the next timer tick
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/// Draw operations shouldn't pause execution until the next timer tick
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pub draw_wait: bool,
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/// DMA instructions `Fx55`/`Fx65` should change I to I + x + 1
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/// DMA instructions `Fx55`/`Fx65` shouldn't change I to I + x + 1
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pub dma_inc: bool,
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/// Indexed jump instructions should go to ADR + v`N` where `N` is high nibble of adr
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/// Indexed jump instructions should go to `adr` + v`a` where `a` is high nibble of `adr`.
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pub stupid_jumps: bool,
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}
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@ -593,42 +593,7 @@ impl CPU {
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// decode opcode
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if let Ok((inc, insn)) = Insn::decode(opcode) {
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self.pc = self.pc.wrapping_add(inc as u16);
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match insn {
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Insn::cls => self.clear_screen(bus),
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Insn::ret => self.ret(bus),
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Insn::jmp { A } => self.jump(A),
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Insn::call { A } => self.call(A, bus),
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Insn::seb { B, x } => self.skip_equals_immediate(x, B),
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Insn::sneb { B, x } => self.skip_not_equals_immediate(x, B),
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Insn::se { y, x } => self.skip_equals(x, y),
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Insn::movb { B, x } => self.load_immediate(x, B),
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Insn::addb { B, x } => self.add_immediate(x, B),
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Insn::mov { x, y } => self.load(x, y),
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Insn::or { y, x } => self.or(x, y),
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Insn::and { y, x } => self.and(x, y),
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Insn::xor { y, x } => self.xor(x, y),
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Insn::add { y, x } => self.add(x, y),
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Insn::sub { y, x } => self.sub(x, y),
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Insn::shr { y, x } => self.shift_right(x, y),
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Insn::bsub { y, x } => self.backwards_sub(x, y),
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Insn::shl { y, x } => self.shift_left(x, y),
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Insn::sne { y, x } => self.skip_not_equals(x, y),
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Insn::movI { A } => self.load_i_immediate(A),
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Insn::jmpr { A } => self.jump_indexed(A),
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Insn::rand { B, x } => self.rand(x, B),
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Insn::draw { x, y, n } => self.draw(x, y, n, bus),
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Insn::sek { x } => self.skip_key_equals(x),
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Insn::snek { x } => self.skip_key_not_equals(x),
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Insn::getdt { x } => self.load_delay_timer(x),
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Insn::waitk { x } => self.wait_for_key(x),
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Insn::setdt { x } => self.store_delay_timer(x),
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Insn::movst { x } => self.store_sound_timer(x),
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Insn::addI { x } => self.add_i(x),
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Insn::font { x } => self.load_sprite(x),
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Insn::bcd { x } => self.bcd_convert(x, bus),
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Insn::dmao { x } => self.store_dma(x, bus),
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Insn::dmai { x } => self.load_dma(x, bus),
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}
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self.execute(bus, insn);
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} else {
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return Err(Error::UnimplementedInstruction {
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word: u16::from_be_bytes(*opcode),
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@ -727,23 +692,65 @@ impl Default for CPU {
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// Below this point, comments may be duplicated per impl' block,
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// since some opcodes handle multiple instructions.
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// | 0aaa | Issues a "System call" (ML routine)
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impl CPU {
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/// Executes a single [Insn]
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#[inline(always)]
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#[rustfmt::skip]
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fn execute(&mut self, bus: &mut Bus, instruction: Insn) {
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match instruction {
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Insn::cls => self.clear_screen(bus),
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Insn::ret => self.ret(bus),
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Insn::jmp { A } => self.jump(A),
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Insn::call { A } => self.call(A, bus),
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Insn::seb { B, x } => self.skip_equals_immediate(x, B),
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Insn::sneb { B, x } => self.skip_not_equals_immediate(x, B),
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Insn::se { y, x } => self.skip_equals(x, y),
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Insn::movb { B, x } => self.load_immediate(x, B),
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Insn::addb { B, x } => self.add_immediate(x, B),
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Insn::mov { x, y } => self.load(x, y),
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Insn::or { y, x } => self.or(x, y),
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Insn::and { y, x } => self.and(x, y),
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Insn::xor { y, x } => self.xor(x, y),
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Insn::add { y, x } => self.add(x, y),
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Insn::sub { y, x } => self.sub(x, y),
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Insn::shr { y, x } => self.shift_right(x, y),
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Insn::bsub { y, x } => self.backwards_sub(x, y),
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Insn::shl { y, x } => self.shift_left(x, y),
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Insn::sne { y, x } => self.skip_not_equals(x, y),
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Insn::movI { A } => self.load_i_immediate(A),
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Insn::jmpr { A } => self.jump_indexed(A),
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Insn::rand { B, x } => self.rand(x, B),
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Insn::draw { x, y, n } => self.draw(x, y, n, bus),
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Insn::sek { x } => self.skip_key_equals(x),
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Insn::snek { x } => self.skip_key_not_equals(x),
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Insn::getdt { x } => self.load_delay_timer(x),
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Insn::waitk { x } => self.wait_for_key(x),
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Insn::setdt { x } => self.store_delay_timer(x),
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Insn::movst { x } => self.store_sound_timer(x),
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Insn::addI { x } => self.add_i(x),
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Insn::font { x } => self.load_sprite(x),
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Insn::bcd { x } => self.bcd_convert(x, bus),
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Insn::dmao { x } => self.store_dma(x, bus),
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Insn::dmai { x } => self.load_dma(x, bus),
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}
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}
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}
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// |`0aaa`| Issues a "System call" (ML routine)
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | 00e0 | Clear screen memory to all 0 |
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// | 00ee | Return from subroutine |
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// |`00e0`| Clear screen memory to all 0 |
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// |`00ee`| Return from subroutine |
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impl CPU {
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/// 00e0: Clears the screen memory to 0
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/// |`00e0`| Clears the screen memory to 0
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#[inline(always)]
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fn clear_screen(&mut self, bus: &mut Bus) {
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if let Some(screen) = bus.get_region_mut(Region::Screen) {
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for byte in screen {
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*byte = 0;
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screen.fill(0);
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}
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}
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}
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/// 00ee: Returns from subroutine
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/// |`00ee`| Returns from subroutine
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#[inline(always)]
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fn ret(&mut self, bus: &impl Read<u16>) {
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self.sp = self.sp.wrapping_add(2);
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@ -751,9 +758,9 @@ impl CPU {
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}
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}
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// | 1aaa | Sets pc to an absolute address
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// |`1aaa`| Sets pc to an absolute address
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impl CPU {
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/// 1aaa: Sets the program counter to an absolute address
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/// |`1aaa`| Sets the program counter to an absolute address
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#[inline(always)]
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fn jump(&mut self, a: Adr) {
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// jump to self == halt
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@ -764,9 +771,9 @@ impl CPU {
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}
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}
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// | 2aaa | Pushes pc onto the stack, then jumps to a
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// |`2aaa`| Pushes pc onto the stack, then jumps to a
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impl CPU {
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/// 2aaa: Pushes pc onto the stack, then jumps to a
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/// |`2aaa`| Pushes pc onto the stack, then jumps to a
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#[inline(always)]
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fn call(&mut self, a: Adr, bus: &mut impl Write<u16>) {
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bus.write(self.sp, self.pc);
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@ -775,9 +782,9 @@ impl CPU {
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}
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}
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// | 3xbb | Skips next instruction if register X == b
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// |`3xbb`| Skips next instruction if register X == b
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impl CPU {
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/// 3xbb: Skips the next instruction if register X == b
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/// |`3xbb`| Skips the next instruction if register X == b
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#[inline(always)]
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fn skip_equals_immediate(&mut self, x: Reg, b: u8) {
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if self.v[x] == b {
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@ -786,9 +793,9 @@ impl CPU {
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}
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}
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// | 4xbb | Skips next instruction if register X != b
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// |`4xbb`| Skips next instruction if register X != b
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impl CPU {
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/// 4xbb: Skips the next instruction if register X != b
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/// |`4xbb`| Skips the next instruction if register X != b
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#[inline(always)]
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fn skip_not_equals_immediate(&mut self, x: Reg, b: u8) {
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if self.v[x] != b {
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@ -797,13 +804,13 @@ impl CPU {
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}
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}
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// | 5xyn | Performs a register-register comparison
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// |`5xyn`| Performs a register-register comparison
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | 5XY0 | Skip next instruction if vX == vY |
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// |`5XY0`| Skip next instruction if vX == vY |
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impl CPU {
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/// 5xy0: Skips the next instruction if register X != register Y
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/// |`5xy0`| Skips the next instruction if register X != register Y
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#[inline(always)]
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fn skip_equals(&mut self, x: Reg, y: Reg) {
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if self.v[x] == self.v[y] {
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@ -812,102 +819,102 @@ impl CPU {
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}
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}
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// | 6xbb | Loads immediate byte b into register vX
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// |`6xbb`| Loads immediate byte b into register vX
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impl CPU {
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/// 6xbb: Loads immediate byte b into register vX
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/// |`6xbb`| Loads immediate byte b into register vX
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#[inline(always)]
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fn load_immediate(&mut self, x: Reg, b: u8) {
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self.v[x] = b;
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}
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}
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// | 7xbb | Adds immediate byte b to register vX
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// |`7xbb`| Adds immediate byte b to register vX
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impl CPU {
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/// 7xbb: Adds immediate byte b to register vX
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/// |`7xbb`| Adds immediate byte b to register vX
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#[inline(always)]
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fn add_immediate(&mut self, x: Reg, b: u8) {
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self.v[x] = self.v[x].wrapping_add(b);
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}
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}
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// | 8xyn | Performs ALU operation
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// |`8xyn`| Performs ALU operation
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | 8xy0 | Y = X |
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// | 8xy1 | X = X | Y |
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// | 8xy2 | X = X & Y |
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// | 8xy3 | X = X ^ Y |
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// | 8xy4 | X = X + Y; Set vF=carry |
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// | 8xy5 | X = X - Y; Set vF=carry |
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// | 8xy6 | X = X >> 1 |
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// | 8xy7 | X = Y - X; Set vF=carry |
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// | 8xyE | X = X << 1 |
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// |`8xy0`| Y = X |
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// |`8xy1`| X = X | Y |
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// |`8xy2`| X = X & Y |
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// |`8xy3`| X = X ^ Y |
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// |`8xy4`| X = X + Y; Set vF=carry |
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// |`8xy5`| X = X - Y; Set vF=carry |
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// |`8xy6`| X = X >> 1 |
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// |`8xy7`| X = Y - X; Set vF=carry |
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// |`8xyE`| X = X << 1 |
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impl CPU {
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/// 8xy0: Loads the value of y into x
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/// |`8xy0`| Loads the value of y into x
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#[inline(always)]
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fn load(&mut self, x: Reg, y: Reg) {
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self.v[x] = self.v[y];
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}
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/// 8xy1: Performs bitwise or of vX and vY, and stores the result in vX
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/// |`8xy1`| Performs bitwise or of vX and vY, and stores the result in vX
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///
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/// # Quirk
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline(always)]
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fn or(&mut self, x: Reg, y: Reg) {
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self.v[x] |= self.v[y];
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if self.flags.quirks.bin_ops {
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if !self.flags.quirks.bin_ops {
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self.v[0xf] = 0;
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}
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}
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/// 8xy2: Performs bitwise and of vX and vY, and stores the result in vX
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/// |`8xy2`| Performs bitwise and of vX and vY, and stores the result in vX
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///
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/// # Quirk
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline(always)]
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fn and(&mut self, x: Reg, y: Reg) {
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self.v[x] &= self.v[y];
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if self.flags.quirks.bin_ops {
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if !self.flags.quirks.bin_ops {
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self.v[0xf] = 0;
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}
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}
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/// 8xy3: Performs bitwise xor of vX and vY, and stores the result in vX
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/// |`8xy3`| Performs bitwise xor of vX and vY, and stores the result in vX
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///
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/// # Quirk
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline(always)]
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fn xor(&mut self, x: Reg, y: Reg) {
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self.v[x] ^= self.v[y];
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if self.flags.quirks.bin_ops {
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if !self.flags.quirks.bin_ops {
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self.v[0xf] = 0;
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}
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}
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/// 8xy4: Performs addition of vX and vY, and stores the result in vX
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/// |`8xy4`| Performs addition of vX and vY, and stores the result in vX
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#[inline(always)]
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fn add(&mut self, x: Reg, y: Reg) {
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let carry;
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(self.v[x], carry) = self.v[x].overflowing_add(self.v[y]);
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self.v[0xf] = carry.into();
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}
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/// 8xy5: Performs subtraction of vX and vY, and stores the result in vX
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/// |`8xy5`| Performs subtraction of vX and vY, and stores the result in vX
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#[inline(always)]
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fn sub(&mut self, x: Reg, y: Reg) {
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let carry;
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(self.v[x], carry) = self.v[x].overflowing_sub(self.v[y]);
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self.v[0xf] = (!carry).into();
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}
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/// 8xy6: Performs bitwise right shift of vX
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/// |`8xy6`| Performs bitwise right shift of vX
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///
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/// # Quirk
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/// On the original chip-8 interpreter, this shifts vY and stores the result in vX
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#[inline(always)]
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fn shift_right(&mut self, x: Reg, y: Reg) {
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let src: Reg = if self.flags.quirks.shift { y } else { x };
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let src: Reg = if self.flags.quirks.shift { x } else { y };
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let shift_out = self.v[src] & 1;
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self.v[x] = self.v[src] >> 1;
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self.v[0xf] = shift_out;
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}
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/// 8xy7: Performs subtraction of vY and vX, and stores the result in vX
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/// |`8xy7`| Performs subtraction of vY and vX, and stores the result in vX
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#[inline(always)]
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fn backwards_sub(&mut self, x: Reg, y: Reg) {
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let carry;
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@ -921,20 +928,20 @@ impl CPU {
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/// and store the result in vX. This behavior was left out, for now.
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#[inline(always)]
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fn shift_left(&mut self, x: Reg, y: Reg) {
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let src: Reg = if self.flags.quirks.shift { y } else { x };
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let src: Reg = if self.flags.quirks.shift { x } else { y };
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let shift_out: u8 = self.v[src] >> 7;
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self.v[x] = self.v[src] << 1;
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self.v[0xf] = shift_out;
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}
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}
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// | 9xyn | Performs a register-register comparison
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// |`9xyn`| Performs a register-register comparison
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | 9XY0 | Skip next instruction if vX != vY |
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// |`9XY0`| Skip next instruction if vX != vY |
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impl CPU {
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/// 9xy0: Skip next instruction if X != y
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/// |`9xy0`| Skip next instruction if X != y
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#[inline(always)]
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fn skip_not_equals(&mut self, x: Reg, y: Reg) {
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if self.v[x] != self.v[y] {
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@ -943,18 +950,18 @@ impl CPU {
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}
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}
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// | Aaaa | Load address #a into register I
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// |`Aaaa`| Load address #a into register I
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impl CPU {
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/// Aadr: Load address #adr into register I
|
||||
/// |`Aadr`| Load address #adr into register I
|
||||
#[inline(always)]
|
||||
fn load_i_immediate(&mut self, a: Adr) {
|
||||
self.i = a;
|
||||
}
|
||||
}
|
||||
|
||||
// | Baaa | Jump to &adr + v0
|
||||
// |`Baaa`| Jump to &adr + v0
|
||||
impl CPU {
|
||||
/// Badr: Jump to &adr + v0
|
||||
/// |`Badr`| Jump to &adr + v0
|
||||
///
|
||||
/// Quirk:
|
||||
/// On the Super-Chip, this does stupid shit
|
||||
@ -969,25 +976,25 @@ impl CPU {
|
||||
}
|
||||
}
|
||||
|
||||
// | Cxbb | Stores a random number & the provided byte into vX
|
||||
// |`Cxbb`| Stores a random number & the provided byte into vX
|
||||
impl CPU {
|
||||
/// Cxbb: Stores a random number & the provided byte into vX
|
||||
/// |`Cxbb`| Stores a random number & the provided byte into vX
|
||||
#[inline(always)]
|
||||
fn rand(&mut self, x: Reg, b: u8) {
|
||||
self.v[x] = random::<u8>() & b;
|
||||
}
|
||||
}
|
||||
|
||||
// | Dxyn | Draws n-byte sprite to the screen at coordinates (vX, vY)
|
||||
// |`Dxyn`| Draws n-byte sprite to the screen at coordinates (vX, vY)
|
||||
impl CPU {
|
||||
/// Dxyn: Draws n-byte sprite to the screen at coordinates (vX, vY)
|
||||
/// |`Dxyn`| Draws n-byte sprite to the screen at coordinates (vX, vY)
|
||||
///
|
||||
/// # Quirk
|
||||
/// On the original chip-8 interpreter, this will wait for a VBI
|
||||
#[inline(always)]
|
||||
fn draw(&mut self, x: Reg, y: Reg, n: Nib, bus: &mut Bus) {
|
||||
let (x, y) = (self.v[x] as u16 % 64, self.v[y] as u16 % 32);
|
||||
if self.flags.quirks.draw_wait {
|
||||
if !self.flags.quirks.draw_wait {
|
||||
self.flags.draw_wait = true;
|
||||
}
|
||||
self.v[0xf] = 0;
|
||||
@ -1015,14 +1022,14 @@ impl CPU {
|
||||
}
|
||||
}
|
||||
|
||||
// | Exbb | Skips instruction on value of keypress
|
||||
// |`Exbb`| Skips instruction on value of keypress
|
||||
//
|
||||
// |opcode| effect |
|
||||
// |------|------------------------------------|
|
||||
// | eX9e | Skip next instruction if key == vX |
|
||||
// | eXa1 | Skip next instruction if key != vX |
|
||||
// |`eX9e`| Skip next instruction if key == vX |
|
||||
// |`eXa1`| Skip next instruction if key != vX |
|
||||
impl CPU {
|
||||
/// Ex9E: Skip next instruction if key == vX
|
||||
/// |`Ex9E`| Skip next instruction if key == vX
|
||||
#[inline(always)]
|
||||
fn skip_key_equals(&mut self, x: Reg) {
|
||||
let x = self.v[x] as usize;
|
||||
@ -1030,7 +1037,7 @@ impl CPU {
|
||||
self.pc += 2;
|
||||
}
|
||||
}
|
||||
/// ExaE: Skip next instruction if key != vX
|
||||
/// |`ExaE`| Skip next instruction if key != vX
|
||||
#[inline(always)]
|
||||
fn skip_key_not_equals(&mut self, x: Reg) {
|
||||
let x = self.v[x] as usize;
|
||||
@ -1040,21 +1047,21 @@ impl CPU {
|
||||
}
|
||||
}
|
||||
|
||||
// | Fxbb | Performs IO
|
||||
// |`Fxbb`| Performs IO
|
||||
//
|
||||
// |opcode| effect |
|
||||
// |------|------------------------------------|
|
||||
// | fX07 | Set vX to value in delay timer |
|
||||
// | fX0a | Wait for input, store key in vX |
|
||||
// | fX15 | Set sound timer to the value in vX |
|
||||
// | fX18 | set delay timer to the value in vX |
|
||||
// | fX1e | Add vX to I |
|
||||
// | fX29 | Load sprite for character x into I |
|
||||
// | fX33 | BCD convert X into I[0..3] |
|
||||
// | fX55 | DMA Stor from I to registers 0..=X |
|
||||
// | fX65 | DMA Load from I to registers 0..=X |
|
||||
// |`fX07`| Set vX to value in delay timer |
|
||||
// |`fX0a`| Wait for input, store key in vX |
|
||||
// |`fX15`| Set sound timer to the value in vX |
|
||||
// |`fX18`| set delay timer to the value in vX |
|
||||
// |`fX1e`| Add vX to I |
|
||||
// |`fX29`| Load sprite for character x into I |
|
||||
// |`fX33`| BCD convert X into I[0..3] |
|
||||
// |`fX55`| DMA Stor from I to registers 0..=X |
|
||||
// |`fX65`| DMA Load from I to registers 0..=X |
|
||||
impl CPU {
|
||||
/// Fx07: Get the current DT, and put it in vX
|
||||
/// |`Fx07`| Get the current DT, and put it in vX
|
||||
/// ```py
|
||||
/// vX = DT
|
||||
/// ```
|
||||
@ -1062,7 +1069,7 @@ impl CPU {
|
||||
fn load_delay_timer(&mut self, x: Reg) {
|
||||
self.v[x] = self.delay as u8;
|
||||
}
|
||||
/// Fx0A: Wait for key, then vX = K
|
||||
/// |`Fx0A`| Wait for key, then vX = K
|
||||
#[inline(always)]
|
||||
fn wait_for_key(&mut self, x: Reg) {
|
||||
if let Some(key) = self.flags.lastkey {
|
||||
@ -1073,7 +1080,7 @@ impl CPU {
|
||||
self.flags.keypause = true;
|
||||
}
|
||||
}
|
||||
/// Fx15: Load vX into DT
|
||||
/// |`Fx15`| Load vX into DT
|
||||
/// ```py
|
||||
/// DT = vX
|
||||
/// ```
|
||||
@ -1081,7 +1088,7 @@ impl CPU {
|
||||
fn store_delay_timer(&mut self, x: Reg) {
|
||||
self.delay = self.v[x] as f64;
|
||||
}
|
||||
/// Fx18: Load vX into ST
|
||||
/// |`Fx18`| Load vX into ST
|
||||
/// ```py
|
||||
/// ST = vX;
|
||||
/// ```
|
||||
@ -1089,7 +1096,7 @@ impl CPU {
|
||||
fn store_sound_timer(&mut self, x: Reg) {
|
||||
self.sound = self.v[x] as f64;
|
||||
}
|
||||
/// Fx1e: Add vX to I,
|
||||
/// |`Fx1e`| Add vX to I,
|
||||
/// ```py
|
||||
/// I += vX;
|
||||
/// ```
|
||||
@ -1097,7 +1104,7 @@ impl CPU {
|
||||
fn add_i(&mut self, x: Reg) {
|
||||
self.i += self.v[x] as u16;
|
||||
}
|
||||
/// Fx29: Load sprite for character x into I
|
||||
/// |`Fx29`| Load sprite for character x into I
|
||||
/// ```py
|
||||
/// I = sprite(X);
|
||||
/// ```
|
||||
@ -1105,7 +1112,7 @@ impl CPU {
|
||||
fn load_sprite(&mut self, x: Reg) {
|
||||
self.i = self.font + (5 * (self.v[x] as Adr % 0x10));
|
||||
}
|
||||
/// Fx33: BCD convert X into I`[0..3]`
|
||||
/// |`Fx33`| BCD convert X into I`[0..3]`
|
||||
#[inline(always)]
|
||||
fn bcd_convert(&mut self, x: Reg, bus: &mut Bus) {
|
||||
let x = self.v[x];
|
||||
@ -1113,7 +1120,7 @@ impl CPU {
|
||||
bus.write(self.i.wrapping_add(1), x / 10 % 10);
|
||||
bus.write(self.i, x / 100 % 10);
|
||||
}
|
||||
/// Fx55: DMA Stor from I to registers 0..=X
|
||||
/// |`Fx55`| DMA Stor from I to registers 0..=X
|
||||
///
|
||||
/// # Quirk
|
||||
/// The original chip-8 interpreter uses I to directly index memory,
|
||||
@ -1129,11 +1136,11 @@ impl CPU {
|
||||
{
|
||||
*value = self.v[reg]
|
||||
}
|
||||
if self.flags.quirks.dma_inc {
|
||||
if !self.flags.quirks.dma_inc {
|
||||
self.i += x as Adr + 1;
|
||||
}
|
||||
}
|
||||
/// Fx65: DMA Load from I to registers 0..=X
|
||||
/// |`Fx65`| DMA Load from I to registers 0..=X
|
||||
///
|
||||
/// # Quirk
|
||||
/// The original chip-8 interpreter uses I to directly index memory,
|
||||
@ -1144,7 +1151,7 @@ impl CPU {
|
||||
for (reg, value) in bus.get(i..=i + x).unwrap_or_default().iter().enumerate() {
|
||||
self.v[reg] = *value;
|
||||
}
|
||||
if self.flags.quirks.dma_inc {
|
||||
if !self.flags.quirks.dma_inc {
|
||||
self.i += x as Adr + 1;
|
||||
}
|
||||
}
|
||||
|
||||
185
src/cpu/tests.rs
185
src/cpu/tests.rs
@ -331,13 +331,36 @@ mod math {
|
||||
}
|
||||
}
|
||||
}
|
||||
mod or {
|
||||
use super::*;
|
||||
|
||||
/// 8xy1: Performs bitwise or of vX and vY, and stores the result in vX
|
||||
// TODO: Test with bin_ops quirk flag set
|
||||
#[test]
|
||||
fn or_inaccurate() {
|
||||
fn or() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
cpu.flags.quirks.bin_ops = false;
|
||||
for word in 0..=0xffff {
|
||||
let (a, b) = (word as u8, (word >> 4) as u8);
|
||||
let expected_result = a | b;
|
||||
for reg in 0..=0xff {
|
||||
let (x, y) = (reg & 0xf, reg >> 4);
|
||||
|
||||
cpu.v[0xf] = 0xc5; // sentinel
|
||||
(cpu.v[x], cpu.v[y]) = (a, b);
|
||||
|
||||
cpu.or(x, y);
|
||||
|
||||
if x != 0xf {
|
||||
assert_eq!(cpu.v[x], if x == y { b } else { expected_result });
|
||||
}
|
||||
assert_eq!(cpu.v[0xf], 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
/// Same test, with [Quirks::bin_ops] flag set
|
||||
#[test]
|
||||
fn or_quirk() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
cpu.flags.quirks.bin_ops = true;
|
||||
for word in 0..=0xffff {
|
||||
let (a, b) = (word as u8, (word >> 4) as u8);
|
||||
let expected_result = a | b;
|
||||
@ -352,13 +375,36 @@ mod math {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mod and {
|
||||
use super::*;
|
||||
/// 8xy2: Performs bitwise and of vX and vY, and stores the result in vX
|
||||
// TODO: Test with bin_ops quirk flag set
|
||||
#[test]
|
||||
fn and_inaccurate() {
|
||||
fn and() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
cpu.flags.quirks.bin_ops = false;
|
||||
for word in 0..=0xffff {
|
||||
let (a, b) = (word as u8, (word >> 4) as u8);
|
||||
let expected_result = a & b;
|
||||
for reg in 0..=0xff {
|
||||
let (x, y) = (reg & 0xf, reg >> 4);
|
||||
|
||||
cpu.v[0xf] = 0xc5; // Sentinel
|
||||
(cpu.v[x], cpu.v[y]) = (a, b);
|
||||
|
||||
cpu.and(x, y);
|
||||
if x != 0xf {
|
||||
assert_eq!(cpu.v[x], if x == y { b } else { expected_result });
|
||||
}
|
||||
assert_eq!(cpu.v[0xf], 0)
|
||||
}
|
||||
}
|
||||
}
|
||||
// The same test with [Quirks::bin_ops] flag set
|
||||
#[test]
|
||||
fn and_quirk() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
cpu.flags.quirks.bin_ops = true;
|
||||
for word in 0..=0xffff {
|
||||
let (a, b) = (word as u8, (word >> 4) as u8);
|
||||
let expected_result = a & b;
|
||||
@ -373,13 +419,36 @@ mod math {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
mod xor {
|
||||
use super::*;
|
||||
|
||||
/// 8xy3: Performs bitwise xor of vX and vY, and stores the result in vX
|
||||
// TODO: Test with bin_ops quirk flag set
|
||||
#[test]
|
||||
fn xor_inaccurate() {
|
||||
fn xor() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
cpu.flags.quirks.bin_ops = false;
|
||||
for word in 0..=0xffff {
|
||||
let (a, b) = (word as u8, (word >> 4) as u8);
|
||||
let expected_result = a ^ b;
|
||||
for reg in 0..=0xff {
|
||||
let (x, y) = (reg & 0xf, reg >> 4);
|
||||
|
||||
cpu.v[0xf] = 0xc5; // Sentinel
|
||||
(cpu.v[x], cpu.v[y]) = (a, b);
|
||||
|
||||
cpu.xor(x, y);
|
||||
if x != 0xf {
|
||||
assert_eq!(cpu.v[x], if x == y { 0 } else { expected_result });
|
||||
}
|
||||
assert_eq!(cpu.v[0xf], 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
// The same test with [Quirks::bin_ops] flag set
|
||||
#[test]
|
||||
fn xor_quirk() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
cpu.flags.quirks.bin_ops = true;
|
||||
for word in 0..=0xffff {
|
||||
let (a, b) = (word as u8, (word >> 4) as u8);
|
||||
let expected_result = a ^ b;
|
||||
@ -394,6 +463,7 @@ mod math {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// 8xy4: Performs addition of vX and vY, and stores the result in vX, carry in vF
|
||||
/// If X is F, *only* stores borrow
|
||||
@ -445,18 +515,19 @@ mod math {
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
mod shift_right {
|
||||
use super::*;
|
||||
/// 8xy6: Performs bitwise right shift of vX, stores carry-out in vF
|
||||
// TODO: Test with authentic flag set
|
||||
#[test]
|
||||
fn shift_right() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
for word in 0..=0xff {
|
||||
for x in 0..=0xf {
|
||||
for reg in 0..=0xff {
|
||||
let (x, y) = (reg & 0xf, reg >> 4);
|
||||
// set the register under test to `word`
|
||||
cpu.v[x] = word;
|
||||
(cpu.v[x], cpu.v[y]) = (0, word);
|
||||
|
||||
cpu.shift_right(x, x);
|
||||
cpu.shift_right(x, y);
|
||||
|
||||
// if the destination is vF, the result was discarded, and only the carry was kept
|
||||
if x != 0xf {
|
||||
@ -467,6 +538,29 @@ mod math {
|
||||
}
|
||||
}
|
||||
}
|
||||
/// The same test, with [Quirks::shift] quirk flag set
|
||||
#[test]
|
||||
fn shift_right_quirk() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
cpu.flags.quirks.shift = true;
|
||||
for word in 0..=0xff {
|
||||
for reg in 0..=0xff {
|
||||
let (x, y) = (reg & 0xf, reg >> 4);
|
||||
// set the register under test to `word`
|
||||
cpu.v[x] = word;
|
||||
|
||||
cpu.shift_right(x, y);
|
||||
|
||||
// if the destination is vF, the result was discarded, and only the carry was kept
|
||||
if x != 0xf {
|
||||
assert_eq!(cpu.v[x], word >> 1);
|
||||
}
|
||||
// The borrow flag for subtraction is inverted
|
||||
assert_eq!(cpu.v[0xf], word & 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// 8xy7: Performs subtraction of vY and vX, and stores the result in vX and ~carry in vF
|
||||
#[test]
|
||||
@ -492,11 +586,35 @@ mod math {
|
||||
}
|
||||
}
|
||||
|
||||
/// 8X_E: Performs bitwise left shift of vX
|
||||
// TODO: Test with authentic flag set
|
||||
mod shift_left {
|
||||
use super::*;
|
||||
#[test]
|
||||
fn shift_left() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
for word in 1..=0xff {
|
||||
for reg in 0..=0xff {
|
||||
let (x, y) = (reg & 0xf, reg >> 4);
|
||||
// set the register under test to `word`
|
||||
(cpu.v[x], cpu.v[y]) = dbg!(0, word);
|
||||
|
||||
cpu.shift_left(x, y);
|
||||
|
||||
// if the destination is vF, the result was discarded, and only the carry was kept
|
||||
if x != 0xf {
|
||||
assert_eq!(cpu.v[x], word << 1);
|
||||
}
|
||||
// The borrow flag for subtraction is inverted
|
||||
assert_eq!(cpu.v[0xf], word >> 7);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// 8X_E: Performs bitwise left shift of vX
|
||||
// TODO: Test with authentic flag set
|
||||
#[test]
|
||||
fn shift_left_quirk() {
|
||||
let (mut cpu, _) = setup_environment();
|
||||
cpu.flags.quirks.shift = true;
|
||||
for word in 0..=0xff {
|
||||
for x in 0..=0xf {
|
||||
// set the register under test to `word`
|
||||
@ -513,6 +631,7 @@ mod math {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Test operations on the index/indirect register, I
|
||||
@ -590,10 +709,10 @@ mod io {
|
||||
screen: include_bytes!("tests/screens/BC_test.ch8/197.bin"),
|
||||
steps: 250,
|
||||
quirks: Quirks {
|
||||
bin_ops: true,
|
||||
shift: false,
|
||||
draw_wait: true,
|
||||
dma_inc: false,
|
||||
bin_ops: false,
|
||||
shift: true,
|
||||
draw_wait: false,
|
||||
dma_inc: true,
|
||||
stupid_jumps: false,
|
||||
},
|
||||
},
|
||||
@ -605,10 +724,10 @@ mod io {
|
||||
screen: include_bytes!("tests/screens/IBM Logo.ch8/20.bin"),
|
||||
steps: 56,
|
||||
quirks: Quirks {
|
||||
bin_ops: true,
|
||||
shift: true,
|
||||
draw_wait: true,
|
||||
dma_inc: true,
|
||||
bin_ops: false,
|
||||
shift: false,
|
||||
draw_wait: false,
|
||||
dma_inc: false,
|
||||
stupid_jumps: false,
|
||||
},
|
||||
},
|
||||
@ -620,11 +739,10 @@ mod io {
|
||||
screen: include_bytes!("tests/screens/1dcell.ch8/123342.bin"),
|
||||
steps: 123342,
|
||||
quirks: Quirks {
|
||||
bin_ops: true,
|
||||
shift: true,
|
||||
draw_wait: false,
|
||||
|
||||
dma_inc: true,
|
||||
bin_ops: false,
|
||||
shift: false,
|
||||
draw_wait: true,
|
||||
dma_inc: false,
|
||||
stupid_jumps: false,
|
||||
},
|
||||
},
|
||||
@ -634,11 +752,10 @@ mod io {
|
||||
screen: include_bytes!("tests/screens/1dcell.ch8/2391162.bin"),
|
||||
steps: 2391162,
|
||||
quirks: Quirks {
|
||||
bin_ops: true,
|
||||
shift: true,
|
||||
draw_wait: false,
|
||||
|
||||
dma_inc: true,
|
||||
bin_ops: false,
|
||||
shift: false,
|
||||
draw_wait: true,
|
||||
dma_inc: false,
|
||||
stupid_jumps: false,
|
||||
},
|
||||
},
|
||||
|
||||
@ -13,7 +13,7 @@ fn run_single_op(op: &[u8]) -> CPU {
|
||||
},
|
||||
);
|
||||
cpu.v = *INDX;
|
||||
cpu.flags.quirks = Quirks::from(true);
|
||||
cpu.flags.quirks = Quirks::from(false);
|
||||
cpu.tick(&mut bus).unwrap(); // will panic if unimplemented
|
||||
cpu
|
||||
}
|
||||
|
||||
@ -45,8 +45,7 @@ fn run_screentest(test: SuiteTest, mut cpu: CPU, mut bus: Bus) {
|
||||
|
||||
#[test]
|
||||
fn splash_screen() {
|
||||
let (mut c, b) = setup_environment();
|
||||
c.flags.quirks = true.into();
|
||||
let (c, b) = setup_environment();
|
||||
run_screentest(
|
||||
SuiteTest {
|
||||
program: include_bytes!("chip8-test-suite/bin/chip8-test-suite.ch8"),
|
||||
@ -59,45 +58,42 @@ fn splash_screen() {
|
||||
|
||||
#[test]
|
||||
fn ibm_logo() {
|
||||
let (mut c, mut b) = setup_environment();
|
||||
c.flags.quirks = true.into();
|
||||
b.write(0x1ffu16, 1u8);
|
||||
let (cpu, mut bus) = setup_environment();
|
||||
bus.write(0x1ffu16, 1u8);
|
||||
run_screentest(
|
||||
SuiteTest {
|
||||
program: include_bytes!("chip8-test-suite/bin/chip8-test-suite.ch8"),
|
||||
screen: include_bytes!("screens/chip8-test-suite/IBM.bin"),
|
||||
},
|
||||
c,
|
||||
b,
|
||||
cpu,
|
||||
bus,
|
||||
)
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn flags_test() {
|
||||
let (mut c, mut b) = setup_environment();
|
||||
c.flags.quirks = true.into();
|
||||
b.write(0x1ffu16, 3u8);
|
||||
let (cpu, mut bus) = setup_environment();
|
||||
bus.write(0x1ffu16, 3u8);
|
||||
run_screentest(
|
||||
SuiteTest {
|
||||
program: include_bytes!("chip8-test-suite/bin/chip8-test-suite.ch8"),
|
||||
screen: include_bytes!("screens/chip8-test-suite/flags.bin"),
|
||||
},
|
||||
c,
|
||||
b,
|
||||
cpu,
|
||||
bus,
|
||||
)
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn quirks_test() {
|
||||
let (mut c, mut b) = setup_environment();
|
||||
c.flags.quirks = true.into();
|
||||
b.write(0x1feu16, 0x0104u16);
|
||||
let (cpu, mut bus) = setup_environment();
|
||||
bus.write(0x1feu16, 0x0104u16);
|
||||
run_screentest(
|
||||
SuiteTest {
|
||||
program: include_bytes!("chip8-test-suite/bin/chip8-test-suite.ch8"),
|
||||
screen: include_bytes!("screens/chip8-test-suite/quirks.bin"),
|
||||
},
|
||||
c,
|
||||
b,
|
||||
cpu,
|
||||
bus,
|
||||
)
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user