lib.rs: Deny (missing docs)
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@ -59,6 +59,7 @@ pub enum Region {
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Screen,
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/// Stack space
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Stack,
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#[doc(hidden)]
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/// Total number of named regions
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Count,
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}
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@ -293,7 +294,7 @@ impl Bus {
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///# Ok(())
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///# }
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/// ```
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/// If there is no Screen region, it will return Err(Error::MissingRegion)
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/// If there is no Screen region, it will return Err([MissingRegion])
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/// ```rust,should_panic
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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11
src/cpu.rs
11
src/cpu.rs
@ -61,14 +61,22 @@ impl Default for Quirks {
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}
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}
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/// Represents flags that aid in operation, but aren't inherent to the CPU
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#[derive(Clone, Debug, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct ControlFlags {
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/// Set when debug (live disassembly) mode enabled
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pub debug: bool,
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/// Set when the emulator is paused by the user and should not update
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pub pause: bool,
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/// Set when the emulator is waiting for a keypress
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pub keypause: bool,
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/// Set when the emulator is waiting for a frame to be drawn
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pub vbi_wait: bool,
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/// Set to the last key that's been *released* after a keypause
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pub lastkey: Option<usize>,
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/// Represents the set of emulator "[Quirks]" to enable
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pub quirks: Quirks,
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/// Represents the number of instructions to run per tick of the internal timer
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pub monotonic: Option<usize>,
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}
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@ -111,6 +119,8 @@ impl ControlFlags {
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/// Represents the internal state of the CPU interpreter
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#[derive(Clone, Debug, PartialEq)]
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pub struct CPU {
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/// Flags that control how the CPU behaves, but which aren't inherent to the
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/// implementation. Includes [Quirks], target IPF, etc.
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pub flags: ControlFlags,
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// memory map info
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screen: Adr,
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@ -468,6 +478,7 @@ impl CPU {
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return self;
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};
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// Convert the elapsed time to 60ths of a second
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let time = self.timer.elapsed().as_secs_f64() * 60.0;
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self.timer = Instant::now();
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if time > 1.0 {
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@ -7,31 +7,38 @@ use super::{Adr, Nib, Reg};
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use owo_colors::{OwoColorize, Style};
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type Ins = Nib;
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/// Extracts the I nibble of an IXYN instruction
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#[inline]
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pub fn i(ins: u16) -> Ins {
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(ins >> 12 & 0xf) as Ins
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}
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/// Extracts the X nibble of an IXYN instruction
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#[inline]
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pub fn x(ins: u16) -> Reg {
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(ins >> 8 & 0xf) as Reg
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}
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/// Extracts the Y nibble of an IXYN instruction
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#[inline]
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pub fn y(ins: u16) -> Reg {
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(ins >> 4 & 0xf) as Reg
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}
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/// Extracts the N nibble of an IXYN instruction
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#[inline]
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pub fn n(ins: u16) -> Nib {
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(ins & 0xf) as Nib
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}
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/// Extracts the B byte of an IXBB instruction
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#[inline]
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pub fn b(ins: u16) -> u8 {
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(ins & 0xff) as u8
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}
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/// Extracts the ADR trinibble of an IADR instruction
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#[inline]
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pub fn a(ins: u16) -> Adr {
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ins & 0x0fff
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}
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/// Disassembles Chip-8 instructions, printing them in the provided [owo_colors::Style]s
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#[derive(Clone, Debug, PartialEq)]
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pub struct Disassemble {
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invalid: Style,
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@ -46,15 +53,15 @@ impl Default for Disassemble {
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// Public API
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impl Disassemble {
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// Returns a new Disassemble with the provided Styles
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/// Returns a new Disassemble with the provided Styles
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pub fn new(invalid: Style, normal: Style) -> Disassemble {
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Disassemble { invalid, normal }
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}
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//
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/// Creates a [DisassembleBuilder], for partial configuration
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pub fn builder() -> DisassembleBuilder {
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DisassembleBuilder::default()
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}
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// Disassemble a single instruction
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/// Disassemble a single instruction
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pub fn instruction(&self, opcode: u16) -> String {
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let (i, x, y, n, b, a) = (
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i(opcode),
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@ -374,6 +381,7 @@ impl Disassemble {
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}
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}
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/// Builder for [Disassemble]rs
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#[derive(Clone, Debug, Default, PartialEq)]
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pub struct DisassembleBuilder {
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invalid: Option<Style>,
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@ -6,20 +6,28 @@
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use crate::bus::Region;
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use thiserror::Error;
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/// Result type, equivalent to [std::result::Result]<T, [enum@Error]>
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pub type Result<T> = std::result::Result<T, Error>;
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/// Error type for Chirp.
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#[derive(Debug, Error)]
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pub enum Error {
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/// Represents an unimplemented operation
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#[error("Unrecognized opcode {word}")]
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UnimplementedInstruction {
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/// The offending word
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word: u16,
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},
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/// The region you asked for was not defined
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#[error("No {region} found on bus")]
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MissingRegion {
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/// The offending [Region]
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region: Region,
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},
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/// Error originated in [std::io]
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#[error(transparent)]
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IoError(#[from] std::io::Error),
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/// Error originated in [minifb]
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#[error(transparent)]
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MinifbError(#[from] minifb::Error),
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}
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@ -1,8 +1,8 @@
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// (c) 2023 John A. Breaux
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// This code is licensed under MIT license (see LICENSE.txt for details)
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#![allow(missing_docs)]
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//! Platform-specific IO/UI code, and some debug functionality.
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//! TODO: Break this into its own crate.
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//! TODO: Destroy this all.
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use std::{
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ffi::OsStr,
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17
src/lib.rs
17
src/lib.rs
@ -1,7 +1,7 @@
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// (c) 2023 John A. Breaux
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// This code is licensed under MIT license (see LICENSE.txt for details)
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#![cfg_attr(feature = "unstable", feature(no_coverage))]
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#![deny(missing_docs)]
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//! This crate implements a Chip-8 interpreter as if it were a real CPU architecture,
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//! to the best of my current knowledge. As it's the first emulator project I've
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//! embarked on, and I'm fairly new to Rust, it's going to be rough around the edges.
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@ -13,12 +13,6 @@ pub mod cpu;
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pub mod error;
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pub mod io;
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#[derive(Clone, Debug, Default, PartialEq)]
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pub struct Chip8 {
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pub cpu: cpu::CPU,
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pub bus: bus::Bus,
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}
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/// Common imports for Chirp
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pub mod prelude {
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pub use super::Chip8;
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@ -29,3 +23,12 @@ pub mod prelude {
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pub use error::Result;
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pub use io::{UIBuilder, *};
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}
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/// Holds the state of a Chip-8
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#[derive(Clone, Debug, Default, PartialEq)]
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pub struct Chip8 {
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/// Contains the registers, flags, and operating state for a single Chip-8
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pub cpu: cpu::CPU,
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/// Contains the memory of a chip-8
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pub bus: bus::Bus,
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}
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