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instruction.rs: Clarify the purpose of Insn

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John 2023-04-29 23:34:28 -05:00
parent 861020a8ab
commit 37b8b96683
1 changed files with 3 additions and 2 deletions
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src/cpu/instruction.rs
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@ -1,7 +1,8 @@
// (c) 2023 John A. Breaux // (c) 2023 John A. Breaux
// This code is licensed under MIT license (see LICENSE for details) // This code is licensed under MIT license (see LICENSE for details)
#![allow(clippy::bad_bit_mask)]
//! Contains the definition of a Chip-8 [Insn] //! Contains the definition of a Chip-8 [Insn]
#![allow(clippy::bad_bit_mask)]
pub mod disassembler; pub mod disassembler;
@ -12,7 +13,7 @@ use std::fmt::Display;
#[allow(non_camel_case_types, non_snake_case, missing_docs)] #[allow(non_camel_case_types, non_snake_case, missing_docs)]
#[derive(Clone, Copy, Debug, InstructionSet, PartialEq, Eq)] #[derive(Clone, Copy, Debug, InstructionSet, PartialEq, Eq)]
#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
/// Implements a Disassembler using imperative_rs /// Represents a Chip-8 Instruction
pub enum Insn { pub enum Insn {
// Base instruction set // Base instruction set
/// | 00e0 | Clear screen memory to 0s /// | 00e0 | Clear screen memory to 0s