From 37b8b96683eaead2adddc941865b06a24e236726 Mon Sep 17 00:00:00 2001 From: John Breaux Date: Sat, 29 Apr 2023 23:34:28 -0500 Subject: [PATCH] instruction.rs: Clarify the purpose of Insn --- src/cpu/instruction.rs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cpu/instruction.rs b/src/cpu/instruction.rs index 89646a7..7c777bd 100644 --- a/src/cpu/instruction.rs +++ b/src/cpu/instruction.rs @@ -1,7 +1,8 @@ // (c) 2023 John A. Breaux // This code is licensed under MIT license (see LICENSE for details) -#![allow(clippy::bad_bit_mask)] + //! Contains the definition of a Chip-8 [Insn] +#![allow(clippy::bad_bit_mask)] pub mod disassembler; @@ -12,7 +13,7 @@ use std::fmt::Display; #[allow(non_camel_case_types, non_snake_case, missing_docs)] #[derive(Clone, Copy, Debug, InstructionSet, PartialEq, Eq)] #[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))] -/// Implements a Disassembler using imperative_rs +/// Represents a Chip-8 Instruction pub enum Insn { // Base instruction set /// | 00e0 | Clear screen memory to 0s