cpu.rs: Refactor instruction implementations
- Use rust standard implementations of overflowing arithmetic - Make draw more concise and readable
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5159afa3fd
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27ac674616
151
src/cpu.rs
151
src/cpu.rs
@ -304,7 +304,6 @@ impl CPU {
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_ => self.unimplemented(opcode),
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},
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_ => unimplemented!("Extracted nibble from byte, got >nibble?"),
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}
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let elapsed = time.elapsed();
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// Print opcode disassembly:
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@ -370,7 +369,12 @@ impl Default for CPU {
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}
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}
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// private implementation
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// | 0aaa | Issues a "System call" (ML routine)
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | 00e0 | Clear screen memory to all 0 |
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// | 00ee | Return from subroutine |
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impl CPU {
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/// Unused instructions
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#[inline]
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@ -397,11 +401,23 @@ impl CPU {
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self.sp = self.sp.wrapping_add(2);
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self.pc = bus.read(self.sp);
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}
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}
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// | 1aaa | Sets pc to an absolute address
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impl CPU {
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/// 1aaa: Sets the program counter to an absolute address
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#[inline]
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fn jump(&mut self, a: Adr) {
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// jump to self == halt
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if a.wrapping_add(2) == self.pc {
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self.flags.pause = true;
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}
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self.pc = a;
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}
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}
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// | 2aaa | Pushes pc onto the stack, then jumps to a
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impl CPU {
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/// 2aaa: Pushes pc onto the stack, then jumps to a
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#[inline]
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fn call(&mut self, a: Adr, bus: &mut impl Write<u16>) {
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@ -409,6 +425,10 @@ impl CPU {
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self.sp = self.sp.wrapping_sub(2);
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self.pc = a;
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}
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}
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// | 3xbb | Skips next instruction if register X == b
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impl CPU {
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/// 3xbb: Skips the next instruction if register X == b
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#[inline]
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fn skip_if_x_equal_byte(&mut self, x: Reg, b: u8) {
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@ -416,6 +436,10 @@ impl CPU {
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self.pc = self.pc.wrapping_add(2);
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}
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}
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}
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// | 4xbb | Skips next instruction if register X != b
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impl CPU {
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/// 4xbb: Skips the next instruction if register X != b
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#[inline]
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fn skip_if_x_not_equal_byte(&mut self, x: Reg, b: u8) {
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@ -423,6 +447,14 @@ impl CPU {
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self.pc = self.pc.wrapping_add(2);
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}
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}
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}
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// | 5xyn | Performs a register-register comparison
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | 5XY0 | Skip next instruction if vX == vY |
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impl CPU {
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/// 5xy0: Skips the next instruction if register X != register Y
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#[inline]
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fn skip_if_x_equal_y(&mut self, x: Reg, y: Reg) {
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@ -430,52 +462,85 @@ impl CPU {
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self.pc = self.pc.wrapping_add(2);
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}
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}
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}
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// | 6xbb | Loads immediate byte b into register vX
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impl CPU {
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/// 6xbb: Loads immediate byte b into register vX
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#[inline]
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fn load_immediate(&mut self, x: Reg, b: u8) {
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self.v[x] = b;
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}
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}
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// | 7xbb | Adds immediate byte b to register vX
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impl CPU {
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/// 7xbb: Adds immediate byte b to register vX
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#[inline]
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fn add_immediate(&mut self, x: Reg, b: u8) {
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self.v[x] = self.v[x].wrapping_add(b);
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}
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/// Set the carry register (vF) after math
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#[inline]
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fn set_carry(&mut self, x: Reg, y: Reg, f: fn(u16, u16) -> u16, inv: bool) -> u8 {
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let sum = f(self.v[x] as u16, self.v[y] as u16);
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self.v[0xf] = if (sum & 0xff00 != 0) ^ inv { 1 } else { 0 };
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(sum & 0xff) as u8
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}
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}
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// | 8xyn | Performs ALU operation
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | 8xy0 | Y = X |
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// | 8xy1 | X = X | Y |
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// | 8xy2 | X = X & Y |
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// | 8xy3 | X = X ^ Y |
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// | 8xy4 | X = X + Y; Set vF=carry |
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// | 8xy5 | X = X - Y; Set vF=carry |
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// | 8xy6 | X = X >> 1 |
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// | 8xy7 | X = Y - X; Set vF=carry |
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// | 8xyE | X = X << 1 |
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impl CPU {
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/// 8xy0: Loads the value of y into x
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#[inline]
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fn load_y_into_x(&mut self, x: Reg, y: Reg) {
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self.v[x] = self.v[y];
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if self.flags.authentic {
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self.v[0xf] = 0;
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}
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}
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/// 8xy1: Performs bitwise or of vX and vY, and stores the result in vX
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#[inline]
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fn x_orequals_y(&mut self, x: Reg, y: Reg) {
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self.v[x] |= self.v[y];
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if self.flags.authentic {
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self.v[0xf] = 0;
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}
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}
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/// 8xy2: Performs bitwise and of vX and vY, and stores the result in vX
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#[inline]
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fn x_andequals_y(&mut self, x: Reg, y: Reg) {
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self.v[x] &= self.v[y];
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if self.flags.authentic {
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self.v[0xf] = 0;
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}
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}
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/// 8xy3: Performs bitwise xor of vX and vY, and stores the result in vX
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#[inline]
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fn x_xorequals_y(&mut self, x: Reg, y: Reg) {
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self.v[x] ^= self.v[y];
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if self.flags.authentic {
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self.v[0xf] = 0;
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}
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}
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/// 8xy4: Performs addition of vX and vY, and stores the result in vX
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#[inline]
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fn x_addequals_y(&mut self, x: Reg, y: Reg) {
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self.v[x] = self.set_carry(x, y, u16::wrapping_add, false);
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let carry;
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(self.v[x], carry) = self.v[x].overflowing_add(self.v[y]);
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self.v[0xf] = carry.into();
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}
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/// 8xy5: Performs subtraction of vX and vY, and stores the result in vX
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#[inline]
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fn x_subequals_y(&mut self, x: Reg, y: Reg) {
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self.v[x] = self.set_carry(x, y, u16::wrapping_sub, true);
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let carry;
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(self.v[x], carry) = self.v[x].overflowing_sub(self.v[y]);
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self.v[0xf] = (!carry).into();
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}
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/// 8xy6: Performs bitwise right shift of vX
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#[inline]
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@ -487,7 +552,9 @@ impl CPU {
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/// 8xy7: Performs subtraction of vY and vX, and stores the result in vX
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#[inline]
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fn backwards_subtract(&mut self, x: Reg, y: Reg) {
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self.v[x] = self.set_carry(y, x, u16::wrapping_sub, true);
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let carry;
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(self.v[x], carry) = self.v[y].overflowing_sub(self.v[x]);
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self.v[0xf] = (!carry).into();
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}
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/// 8X_E: Performs bitwise left shift of vX
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#[inline]
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@ -496,7 +563,14 @@ impl CPU {
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self.v[x] <<= 1;
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self.v[0xf] = shift_out;
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}
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}
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// | 9xyn | Performs a register-register comparison
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | 9XY0 | Skip next instruction if vX != vY |
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impl CPU {
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/// 9xy0: Skip next instruction if X != y
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#[inline]
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fn skip_if_x_not_equal_y(&mut self, x: Reg, y: Reg) {
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@ -504,33 +578,51 @@ impl CPU {
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self.pc = self.pc.wrapping_add(2);
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}
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}
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}
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// | Aaaa | Load address #a into register I
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impl CPU {
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/// Aadr: Load address #adr into register I
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#[inline]
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fn load_indirect_register(&mut self, a: Adr) {
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self.i = a;
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}
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}
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// | Baaa | Jump to &adr + v0
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impl CPU {
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/// Badr: Jump to &adr + v0
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#[inline]
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fn jump_indexed(&mut self, a: Adr) {
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self.pc = a.wrapping_add(self.v[0] as Adr);
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}
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}
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// | Cxbb | Stores a random number + the provided byte into vX
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impl CPU {
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/// Cxbb: Stores a random number & the provided byte into vX
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#[inline]
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fn rand(&mut self, x: Reg, b: u8) {
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self.v[x] = random::<u8>() & b;
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}
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}
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// | Dxyn | Draws n-byte sprite to the screen at coordinates (vX, vY)
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impl CPU {
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/// Dxyn: Draws n-byte sprite to the screen at coordinates (vX, vY)
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#[inline]
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fn draw(&mut self, x: Reg, y: Reg, n: Nib, bus: &mut Bus) {
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// println!("{}", format_args!("draw\t#{n:x}, (x: {:x}, y: {:x})", self.v[x], self.v[y]).green());
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let (x, y) = (self.v[x], self.v[y]);
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let (x, y) = (self.v[x] as u16, self.v[y] as u16);
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self.v[0xf] = 0;
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for byte in 0..n as u16 {
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if y + byte > 32 {
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return;
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}
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// Calculate the lower bound address based on the X,Y position on the screen
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let addr = ((y as u16 + byte) * 8) + (x / 8) as u16 + self.screen;
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let addr = (y + byte) * 8 + (x & 0x3f) / 8 + self.screen;
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// Read a byte of sprite data into a u16, and shift it x % 8 bits
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let sprite: u8 = bus.read(self.i + byte);
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let sprite = (sprite as u16) << 1 + (7 - x % 8);
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let sprite = (sprite as u16) << 8 - (x & 7) & if x % 64 > 56 { 0xff00 } else { 0xffff };
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// Read a u16 from the bus containing the two bytes which might need to be updated
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let mut screen: u16 = bus.read(addr);
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// Save the bits-toggled-off flag if necessary
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@ -539,10 +631,19 @@ impl CPU {
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}
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// Update the screen word by XORing the sprite byte
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screen ^= sprite;
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// Save the result back to the screen
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// Save the result to the screen
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bus.write(addr, screen);
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}
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}
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}
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// | Exbb | Skips instruction on value of keypress
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | eX9e | Skip next instruction if key == #X |
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// | eXa1 | Skip next instruction if key != #X |
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impl CPU {
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/// Ex9E: Skip next instruction if key == #X
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#[inline]
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fn skip_if_key_equals_x(&mut self, x: Reg) {
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@ -559,6 +660,22 @@ impl CPU {
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self.pc += 2;
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}
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}
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}
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// | Fxbb | Performs IO
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//
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// |opcode| effect |
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// |------|------------------------------------|
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// | fX07 | Set vX to value in delay timer |
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// | fX0a | Wait for input, store in vX m |
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// | fX15 | Set sound timer to the value in vX |
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// | fX18 | set delay timer to the value in vX |
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// | fX1e | Add x to I |
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// | fX29 | Load sprite for character x into I |
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// | fX33 | BCD convert X into I[0..3] |
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// | fX55 | DMA Stor from I to registers 0..X |
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// | fX65 | DMA Load from I to registers 0..X |
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impl CPU {
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/// Fx07: Get the current DT, and put it in vX
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/// ```py
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/// vX = DT
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