cpu.rs: Actually derive (De)Serialize if feature=serde
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@ -37,6 +37,7 @@ type Nib = u8;
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/// Represents the internal state of the CPU interpreter
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/// Represents the internal state of the CPU interpreter
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#[derive(Clone, PartialEq)]
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#[derive(Clone, PartialEq)]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct CPU {
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pub struct CPU {
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/// Flags that control how the CPU behaves, but which aren't inherent to the
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/// Flags that control how the CPU behaves, but which aren't inherent to the
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/// chip-8. Includes [Quirks], target IPF, etc.
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/// chip-8. Includes [Quirks], target IPF, etc.
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@ -57,6 +58,7 @@ pub struct CPU {
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// Execution data
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// Execution data
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cycle: usize,
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cycle: usize,
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breakpoints: Vec<Adr>,
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breakpoints: Vec<Adr>,
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#[cfg_attr(feature = "serde", serde(skip))]
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disassembler: Dis,
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disassembler: Dis,
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}
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}
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@ -81,6 +81,7 @@ impl Get<u8> for Bus {
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/// Represents a named region in memory
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/// Represents a named region in memory
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#[non_exhaustive]
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#[non_exhaustive]
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#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub enum Region {
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pub enum Region {
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/// Character ROM (but writable!)
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/// Character ROM (but writable!)
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Charset,
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Charset,
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@ -110,6 +111,7 @@ impl Display for Region {
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/// Stores memory in a series of named regions with ranges
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/// Stores memory in a series of named regions with ranges
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#[derive(Clone, Debug, Default, PartialEq)]
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#[derive(Clone, Debug, Default, PartialEq)]
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#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
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pub struct Bus {
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pub struct Bus {
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memory: Vec<u8>,
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memory: Vec<u8>,
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region: [Option<Range<usize>>; Region::Count as usize],
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region: [Option<Range<usize>>; Region::Count as usize],
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