diff --git a/src/cpu.rs b/src/cpu.rs
index e2f9901..2f466c6 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -37,6 +37,7 @@ type Nib = u8;
 
 /// Represents the internal state of the CPU interpreter
 #[derive(Clone, PartialEq)]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct CPU {
     /// Flags that control how the CPU behaves, but which aren't inherent to the
     /// chip-8. Includes [Quirks], target IPF, etc.
@@ -57,6 +58,7 @@ pub struct CPU {
     // Execution data
     cycle: usize,
     breakpoints: Vec<Adr>,
+    #[cfg_attr(feature = "serde", serde(skip))]
     disassembler: Dis,
 }
 
diff --git a/src/cpu/bus.rs b/src/cpu/bus.rs
index 247e834..9caad76 100644
--- a/src/cpu/bus.rs
+++ b/src/cpu/bus.rs
@@ -81,6 +81,7 @@ impl Get<u8> for Bus {
 /// Represents a named region in memory
 #[non_exhaustive]
 #[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub enum Region {
     /// Character ROM (but writable!)
     Charset,
@@ -110,6 +111,7 @@ impl Display for Region {
 
 /// Stores memory in a series of named regions with ranges
 #[derive(Clone, Debug, Default, PartialEq)]
+#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
 pub struct Bus {
     memory: Vec<u8>,
     region: [Option<Range<usize>>; Region::Count as usize],