Bweh/notes/instruction_set.md
2024-06-22 07:34:17 -05:00

4.8 KiB

Instruction Encodings

Mnemonic 7 6 5 4 3 2 1 0
r8 x x x
r8(alt) x x x
r16 x x
r16stk x x
r16mem x x
cond x x
b3 x x x
tgt3 x x x
u8
imm16

Block 1 : Uncategorized

7 6 5 4 3 2 1 0 Mnemonic
nop
1 1 jr u8
1 C C jr cond(C), u8
7 6 5 4 3 2 1 0 Mnemonic
1
1
1 1
1
1 1
1 1
1 1 1

Block 1: 8-bit r2r loads

7 6 5 4 3 2 1 0 Mnemonic
1 1 1 1 1 halt
1 D D D S S S ld rD, rS

Block 2: 8-bit arithmetic

7 6 5 4 3 2 1 0 Mnemonic
1 R R R add a, R
1 1 R R R adc a, R
1 1 R R R sub a, R
1 1 1 R R R sbc a, R
1 1 R R R and a, R
1 1 1 R R R or a, R
1 1 1 R R R xor a, R
1 1 1 1 R R R cp a, R

Block 3: Etc.

Table 0

7 6 5 4 3 2 1 0 Mnemonic
1 1 C C ret cond(C)
1 1 1 ldh [ff00 + u8], a
1 1 1 1 add sp, u8
1 1 1 1 ldh a, [ff00 + u8]
1 1 1 1 1 ldh HL, [c]

Table 1

7 6 5 4 3 2 1 0 Mnemonic
1 1 R R 1 pop r16stk(R)
1 1 1 1 ret
1 1 1 1 1 reti
1 1 1 1 1 jp hl
1 1 1 1 1 1 ld sp, hl

Table 2

7 6 5 4 3 2 1 0 Mnemonic
1 1 C C 1 jp cond(C), imm16
1 1 1 1 ld [c], a
1 1 1 1 1 ld [imm16], a
1 1 1 1 1 ld a, [c]
1 1 1 1 1 1 ld a, [imm16]

Table 3

7 6 5 4 3 2 1 0 Mnemonic
1 1 1 1 jp imm16
1 1 1 1 1 Prefix xCB
... Invalid (No opcode fetch)
1 1 1 1 1 1 di
1 1 1 1 1 1 1 ei

Table 4

7 6 5 4 3 2 1 0 Mnemonic
1 1 C C 1 call cond(C), imm16
1 1 1 X Y 1 Invalid (No opcode fetch)

Table 5

7 6 5 4 3 2 1 0 Mnemonic
1 1 R R 1 1 push r16stk(R)
1 1 1 1 1 call imm16
1 1 X Y 1 1 1 if X

Table 6: Arithmetic with 8-bit immediate

7 6 5 4 3 2 1 0 Mnemonic
1 1 1 1 add a, u8
1 1 1 1 1 adc a, u8
1 1 1 1 1 sub a, u8
1 1 1 1 1 1 sbc a, u8
1 1 1 1 1 and a, u8
1 1 1 1 1 1 xor a, u8
1 1 1 1 1 1 or a, u8
1 1 1 1 1 1 1 cp a, u8

Table 7: Reset vectors

7 6 5 4 3 2 1 0 Mnemonic
1 1 T T T 1 1 1 rst (T * 8)

CB-prefix instructions:

7 6 5 4 3 2 1 0 Mnemonic
R R R rlc R
1 R R R rrc R
1 R R R rl R
1 1 R R R rr R
1 R R R sla R
1 1 R R R sra R
1 1 R R R swap R
1 1 1 R R R srl R
7 6 5 4 3 2 1 Mnemonic
1 i i i R R R bit i, R
1 i i i R R R res i, R
1 1 i i i R R R set i, R