Implement ADD16
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10
src/cpu.rs
10
src/cpu.rs
@ -470,9 +470,13 @@ mod instructions {
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Ok(())
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}
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pub fn add16(&mut self, reg: R16) -> IResult {
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let hl = self.hl.wide().0.to_le_bytes();
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let addn = self[reg].0.to_le_bytes();
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eprintln!("Add {hl:?} to {addn:?} and store the half- and full-carry flags");
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let (value, h) = (self[reg], self[R8::H].0);
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let value_h = (value.0 >> 8) as u8;
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let hc = half_carry_add(value_h, h);
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let carry = h.overflowing_add(value_h).1;
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self.set_n(false).set_h(hc).set_c(carry);
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*self.hl.wide_mut() += value;
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Ok(())
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}
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#[allow(unused)]
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