diff --git a/src/cpu.rs b/src/cpu.rs
index a63536a..1b5e46a 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -470,9 +470,13 @@ mod instructions {
             Ok(())
         }
         pub fn add16(&mut self, reg: R16) -> IResult {
-            let hl = self.hl.wide().0.to_le_bytes();
-            let addn = self[reg].0.to_le_bytes();
-            eprintln!("Add {hl:?} to {addn:?} and store the half- and full-carry flags");
+            let (value, h) = (self[reg], self[R8::H].0);
+            let value_h = (value.0 >> 8) as u8;
+            let hc = half_carry_add(value_h, h);
+            let carry = h.overflowing_add(value_h).1;
+            self.set_n(false).set_h(hc).set_c(carry);
+
+            *self.hl.wide_mut() += value;
             Ok(())
         }
         #[allow(unused)]