j/Bweh
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

CPU: track total M-cycles

Browse Source
This commit is contained in:
John 2024-07-09 01:24:08 -05:00
parent 060a6b068b
commit 6755d318ba
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu.rs
View File

@ -68,6 +68,7 @@ pub struct CPU {
hl: SplitRegister,
/// The number of processor cycles executed in the last instruction
m_cycles: u8,
total_cycles: usize,
/// [Interrupt Master Enable](https://gbdev.io/pandocs/Interrupts.html#ime-interrupt-master-enable-flag-write-only)
ime: Ime,
/// The set of breakpoints
@ -244,8 +245,10 @@ impl CPU {
}
/// Waits one M-Cycle (does not delay)
#[inline]
pub fn wait(&mut self) -> &mut Self {
self.m_cycles += 1;
self.total_cycles = self.total_cycles.wrapping_add(1);
self
}
}
@ -1146,16 +1149,15 @@ impl IndexMut<R16Stack> for CPU {
impl Display for CPU {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
#[rustfmt::skip]
let Self { ir, sp, pc, af, bc, de, hl, m_cycles, ime, breakpoints } = self;
let Self { ir, sp, pc, af, bc, de, hl, m_cycles, total_cycles, ime, breakpoints } = self;
writeln!(f, "Current instruction: {ir}\nPC: {pc:04x}\nSP: {sp:04x}")?;
writeln!(f, "A: {:02x}, F: {}", af.hi(), flag!(af, z, n, h, c))?;
// writeln!(f, "A: {:02x}, F: {:04b}", af.hi(), af.lo() >> 4)?;
writeln!(f, "B: {:02x}, C: {:02x}", bc.hi(), bc.lo())?;
writeln!(f, "D: {:02x}, E: {:02x}", de.hi(), de.lo())?;
writeln!(f, "H: {:02x}, L: {:02x}", hl.hi(), hl.lo())?;
write!(
f,
"Cycles: {m_cycles}\nInterrupts {}",
"Cycles: {total_cycles} ({m_cycles})\nInterrupts {}",
match ime {
Ime::Disabled => "Disabled",
Ime::ShouldEnable => "Should be Enabled",