From fd417afba0ec296e3889706133d82ecbc48018b2 Mon Sep 17 00:00:00 2001 From: John Breaux Date: Wed, 4 Oct 2023 04:31:43 -0500 Subject: [PATCH] opcode: Not all single-operand instructions take a width parameter --- src/parser/instruction/opcode.rs | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/parser/instruction/opcode.rs b/src/parser/instruction/opcode.rs index 8100e60..f4d8488 100644 --- a/src/parser/instruction/opcode.rs +++ b/src/parser/instruction/opcode.rs @@ -77,9 +77,11 @@ impl Opcode { use Register as Reg; use {PrimaryOperand as Src, SecondaryOperand as Dst}; match self { - Self::Rrc | Self::Swpb | Self::Rra | Self::Sxt | Self::Push | Self::Call | Self::Reti => { - (self, Enc::single().end()) - } + Self::Rrc | Self::Rra | Self::Push => (self, Enc::single().end()), + // these instructions do not take a width specifier (though they may still behave properly) + Self::Swpb | Self::Sxt | Self::Call => (self, Enc::single().width(false).end()), + // `reti` does not take any operands. + Self::Reti => (self, Enc::single().operand(Src::Direct(Reg::pc)).end()), Self::Jnz | Self::Jz | Self::Jnc | Self::Jc | Self::Jn | Self::Jge | Self::Jl | Self::Jmp => { (self, Enc::jump().end()) }