v0.3.0: Total overhaul

- Everything has been rewritten
- Modularity is improved somewhat
  - No dependency injection in preprocessor/parser, though
- There are now early and late constant evaluation engines
  - This engine allows for by-value access to already-assembled code
  - Performs basic math operations, remainder, bitwise logic, bit shifts, negation, and bit inversion
  - Also allows for indexing into already-generated code using pointer-arithmetic syntax: `*(&main + 10)`. This is subject to change? It's clunky, and only allows word-aligned access. However, this rewrite is taking far too long, so I'll call the bikeshedding here.
  - Pretty sure this constant evaluation is computationally equivalent to Deadfish?
This commit is contained in:
2024-01-30 05:27:12 -06:00
parent e4a1b889c2
commit fc8f8b9622
44 changed files with 3119 additions and 3055 deletions

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@@ -1,136 +0,0 @@
//! Simple frontend for the assembler
#![feature(decl_macro)]
use argp::parse_args_or_exit;
use msp430_asm::preamble::*;
use std::{
error::Error,
io::{stdin, IsTerminal, Read},
};
fn main() -> Result<(), Box<dyn Error>> {
let mut buf = String::new();
if let Some(file) = parse_args_or_exit::<args::Args>(argp::DEFAULT).file {
buf = std::fs::read_to_string(file)?;
} else if !stdin().is_terminal() {
// if stdin is not a terminal, don't parsecheck each line.
stdin().lock().read_to_string(&mut buf)?;
} else {
// if stdin is a terminal, enter parse-checked REPL mode.
repl::repl(&mut buf)?;
}
asm(&buf)
}
mod args {
use argp::FromArgs;
use std::path::PathBuf;
/// Assembles MSP430 assembly into 16-bit little-endian machine code. \
/// If used interactively, syntax is checked on a per-line basis.
#[derive(Debug, FromArgs)]
pub struct Args {
/// File to load. If not provided, takes input from stdin.
#[argp(option, short = 'f')]
pub file: Option<PathBuf>,
}
}
mod repl {
use super::*;
use anes::{Color, MoveCursorToPreviousLine, ResetAttributes, SetForegroundColor};
use msp430_asm::{
assembler::error::AssemblyError, error::Error as MspError, lexer::error::LexError, parser::error::ParseError,
};
use std::io::{stderr, Write};
macro color ($color: expr, $fmt: literal, $($str: expr),*) {
format_args!(concat!("{}", $fmt, "{}"), ::anes::SetForegroundColor($color),$($str,)* ::anes::ResetAttributes)
}
macro linenr($n: expr) {
format_args!("{:4}: ", $n)
}
macro printflush ($($x: expr),+) {
{print!($($x),+); let _ = ::std::io::stdout().flush();}
}
macro move_cursor($x:expr, $y:expr) {
format_args!("{}{}", ::anes::MoveCursorToPreviousLine($x), "")
}
pub fn repl(buf: &mut String) -> Result<(), Box<dyn Error>> {
let mut line = String::new();
let mut linenr = 1;
println!(
"{}{} v{}{}",
SetForegroundColor(Color::DarkGray),
env!("CARGO_BIN_NAME"),
env!("CARGO_PKG_VERSION"),
ResetAttributes
);
printflush!("{}", linenr!(linenr));
while let Ok(len) = stdin().read_line(&mut line) {
match len {
0 => break, // No newline (reached EOF)
1 => continue, // Line is empty
_ => (),
}
// Try to parse this line in isolation (this restricts preprocessing)
match Parser::default().parse(&line) {
Err(error) => errpp(&line, linenr, &error.into()),
Ok(_) => {
okpp(&line, linenr);
*buf += &line;
linenr += 1;
}
}
line.clear();
printflush!("{}", linenr!(linenr));
}
println!();
Ok(())
}
fn okpp(line: &str, linenr: i32) {
println!("{}{}{}", move_cursor!(1, 5), color!(Color::Green, "{:4}", linenr!(linenr)), line.trim_end(),);
}
/// Pretty-prints a line error
fn errpp(line: &str, linenr: i32, err: &msp430_asm::error::Error) {
if stderr().is_terminal() {
let line = line.trim_end();
eprint!("{}{}", MoveCursorToPreviousLine(1), color!(Color::Red, "{}", linenr!(linenr)));
match err {
// TODO: use a recursive enum to store all valid states
MspError::LexError(LexError::Contextual(c, e))
| MspError::ParseError(ParseError::LexError(LexError::Contextual(c, e)))
| MspError::AssemblyError(AssemblyError::ParseError(ParseError::LexError(LexError::Contextual(
c,
e,
)))) => {
let (start, end) = line.split_at(c.position() - 1);
eprintln!("{start}{} ({e})", color!(Color::Red, "{}", end));
}
_ => {
eprintln!("{} ({err})", color!(Color::Red, "{}", line));
}
}
} else {
eprintln!("{} ({err})", line.trim())
}
}
}
// Parses and assembles a buffer, then prints it in hex to stdout
fn asm(buf: &str) -> Result<(), Box<dyn Error>> {
match Assembler::assemble(&Parser::default().parse(&buf)?) {
Err(error) => println!("{error}"),
Ok(out) => {
for word in out {
print!("{:04x} ", word.swap_bytes())
}
println!();
}
}
Ok(())
}

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@@ -1,222 +1,224 @@
//! TODO: rewrite for v0.3.0
use super::*;
/// Creates a [Parsable] implementation for an enum whose variants
/// are named after other [Parsable] items
macro make_parsable($(#[$meta:meta])* $vis:vis enum $id:ident {$($(#[$vmeta:meta])*$v:ident),*$(,)?}) {
$( #[$meta] )* $vis enum $id {$($(#[$vmeta])*$v($v),)* }
impl ::msp430_asm::parser::parsable::Parsable for $id {
fn parse<'text, T>(p: &Parser, stream: &mut T) -> Result<Self, ParseError>
where T: TokenStream<'text> {
$(if let Some(v) = Parsable::try_parse(p, stream)? { Ok(Self::$v(v)) } else )*
{ Err(ParseError::UnrecognizedDirective("".into())) }
}
}
impl TryFrom<&str> for $id {
type Error = ParseError;
fn try_from(value: &str) -> Result<Self, Self::Error> {
Parsable::parse(&Parser::default(), &mut Tokenizer::new(value).ignore(Type::Space).preprocessed())
}
}
}
make_parsable! {
#[derive(Debug)]
pub enum SyntaxFragment {
Opcode,
PrimaryOperand,
Number,
}
}
// /// Creates a [Parsable] implementation for an enum whose variants
// /// are named after other [Parsable] items
// macro make_parsable($(#[$meta:meta])* $vis:vis enum $id:ident {$($(#[$vmeta:meta])*$v:ident),*$(,)?}) {
// $( #[$meta] )* $vis enum $id {$($(#[$vmeta])*$v($v),)* }
// impl ::msp430_asm::parser::parsable::Parsable for $id {
// fn parse<'text, T>(p: &Parser, stream: &mut T) -> Result<Self, ParseError>
// where T: TokenStream<'text> {
// $(if let Some(v) = Parsable::try_parse(p, stream)? { Ok(Self::$v(v)) } else )*
// { Err(ParseError::UnrecognizedDirective("".into())) }
// }
// }
// impl TryFrom<&str> for $id {
// type Error = ParseError;
// fn try_from(value: &str) -> Result<Self, Self::Error> {
// Parsable::parse(&Parser::default(), &mut Tokenizer::new(value).ignore(Type::Space).preprocessed())
// }
// }
// }
impl SyntaxFragment {
pub fn info(&self) {
match self {
SyntaxFragment::Opcode(o) => Self::opcode_info(o),
SyntaxFragment::PrimaryOperand(o) => Self::operand_info(o),
SyntaxFragment::Number(n) => println!("The number {n}"),
}
}
fn opcode_info(o: &Opcode) {
let (desc, as_rust) = usage(o);
println!("Usage: {o}{}\n{desc} ( {as_rust} )", params(o));
footer!("https://mspgcc.sourceforge.net/manual/x223.html");
}
// TODO: re-enable full instruction decoding
// fn encoding_info(e: &Encoding) {
// match e {
// Encoding::Single { dst, .. } => Self::operand_info(dst),
// Encoding::Jump { target } => println!("Jumps to (pc + {target})"),
// Encoding::Double { src, dst, .. } => {
// Self::operand_info(src);
// Self::operand_info(&dst.clone().into())
// }
// }
// }
fn operand_info(o: &PrimaryOperand) {
match o {
PrimaryOperand::Direct(r) => Self::register_info(r),
PrimaryOperand::Indirect(r) => {
Self::register_info(r);
println!("Indirect addressing mode: use data pointed to by {r}");
}
PrimaryOperand::PostInc(r) => {
Self::register_info(r);
println!("Indirect post-increment mode: use data pointed to by {r}, then increment {r}");
}
PrimaryOperand::Indexed(r, n) => {
Self::register_info(r);
println!("Indexed mode: use the data at {r}[{n}]");
}
PrimaryOperand::Relative(_) => return,
PrimaryOperand::Absolute(n) => println!("Absolute mode: use the data at absolute address {n}"),
PrimaryOperand::Immediate(n) => println!("Immediate mode: the constant {n}"),
PrimaryOperand::Four => println!("#4 mode: Immediate 4 is encoded @sr"),
PrimaryOperand::Eight => println!("#8 mode: Immediate 8 is encoded @sr+"),
PrimaryOperand::Zero => println!("#0 mode: Immediate 0 is encoded cg (r3)"),
PrimaryOperand::One => println!("#1 mode: Immediate 1 is encoded _(cg), where _ is a nonexistent ext-word"),
PrimaryOperand::Two => println!("#2 mode: Immediate 2 is encoded @cg"),
PrimaryOperand::MinusOne => println!("#-1 mode: the all-ones constant, is encoded @cg+"),
}
footer!("https://mspgcc.sourceforge.net/manual/x82.html");
}
fn register_info(r: &Register) {
use Register as Re;
match r {
Re::pc => println!("pc (r0) is the Program Counter. Post-increment addressing will increase it by 2."),
Re::sp => println!("sp (r1) is the Stack Pointer. Post-increment addressing will increase it by 2."),
Re::sr => println!(
"sr (r2) is the Status Register. It has arithmetic flags: oVerflow, Negative, Zero, and Carry;\nInterrupt Enable; and toggles for various clock/sleep functions.\n8\t7\t6\t5\t4\t3\t2\t1\t0\nV\tSCG1\tSCG1\tOSCOFF\tCPUOFF\tGIE\tN\tZ\tC",
),
Re::cg => println!("cg (r3) is the Constant Generator. It's hard-wired to zero."),
Re::r4 | Re::r5 | Re::r6 | Re::r7 | Re::r8 | Re::r9 | Re::r10 | Re::r11 => {
println!("{r} is a callee-saved general purpose register.")
}
Re::r12 | Re::r13 | Re::r14 | Re::r15 => {
println!("{r} is a caller-saved general purpose register, allowed for return values.")
}
}
}
}
// make_parsable! {
// #[derive(Debug)]
// pub enum SyntaxFragment {
// Opcode,
// PrimaryOperand,
// Number,
// }
// }
// Gets parameter usage information from the opcode's EncodingParser
pub fn params(opcode: &Opcode) -> &'static str {
match opcode.resolve().1 {
EncodingParser::Jump { target: None } => " target (relative address or label)",
EncodingParser::Single { width: None, dst: None } => "[.b] dst",
EncodingParser::Single { dst: None, .. } => " dst",
EncodingParser::Double { src: None, dst: None, .. } => "[.b] src, dst",
EncodingParser::Double { src: None, .. } => "[.b] src",
EncodingParser::Double { dst: None, .. } => "[.b] dst",
EncodingParser::Double { .. } => "[.b]",
EncodingParser::Reflexive { reg: None, .. } => "[.b] dst",
_ => "",
}
}
// impl SyntaxFragment {
// pub fn info(&self) {
// match self {
// SyntaxFragment::Opcode(o) => Self::opcode_info(o),
// SyntaxFragment::PrimaryOperand(o) => Self::operand_info(o),
// SyntaxFragment::Number(n) => println!("The number {n}"),
// }
// }
// fn opcode_info(o: &Opcode) {
// let (desc, as_rust) = usage(o);
// println!("Usage: {o}{}\n{desc} ( {as_rust} )", params(o));
// footer!("https://mspgcc.sourceforge.net/manual/x223.html");
// }
// // TODO: re-enable full instruction decoding
// // fn encoding_info(e: &Encoding) {
// // match e {
// // Encoding::Single { dst, .. } => Self::operand_info(dst),
// // Encoding::Jump { target } => println!("Jumps to (pc + {target})"),
// // Encoding::Double { src, dst, .. } => {
// // Self::operand_info(src);
// // Self::operand_info(&dst.clone().into())
// // }
// // }
// // }
// fn operand_info(o: &PrimaryOperand) {
// match o {
// PrimaryOperand::Direct(r) => Self::register_info(r),
// PrimaryOperand::Indirect(r) => {
// Self::register_info(r);
// println!("Indirect addressing mode: use data pointed to by {r}");
// }
// PrimaryOperand::PostInc(r) => {
// Self::register_info(r);
// println!("Indirect post-increment mode: use data pointed to by {r}, then increment {r}");
// }
// PrimaryOperand::Indexed(r, n) => {
// Self::register_info(r);
// println!("Indexed mode: use the data at {r}[{n}]");
// }
// PrimaryOperand::Relative(_) => return,
// PrimaryOperand::Absolute(n) => println!("Absolute mode: use the data at absolute address {n}"),
// PrimaryOperand::Immediate(n) => println!("Immediate mode: the constant {n}"),
// PrimaryOperand::Four => println!("#4 mode: Immediate 4 is encoded @sr"),
// PrimaryOperand::Eight => println!("#8 mode: Immediate 8 is encoded @sr+"),
// PrimaryOperand::Zero => println!("#0 mode: Immediate 0 is encoded cg (r3)"),
// PrimaryOperand::One => println!("#1 mode: Immediate 1 is encoded _(cg), where _ is a nonexistent ext-word"),
// PrimaryOperand::Two => println!("#2 mode: Immediate 2 is encoded @cg"),
// PrimaryOperand::MinusOne => println!("#-1 mode: the all-ones constant, is encoded @cg+"),
// }
// footer!("https://mspgcc.sourceforge.net/manual/x82.html");
// }
// fn register_info(r: &Register) {
// use Register as Re;
// match r {
// Re::pc => println!("pc (r0) is the Program Counter. Post-increment addressing will increase it by 2."),
// Re::sp => println!("sp (r1) is the Stack Pointer. Post-increment addressing will increase it by 2."),
// Re::sr => println!(
// "sr (r2) is the Status Register. It has arithmetic flags: oVerflow, Negative, Zero, and Carry;\nInterrupt Enable; and toggles for various clock/sleep functions.\n8\t7\t6\t5\t4\t3\t2\t1\t0\nV\tSCG1\tSCG1\tOSCOFF\tCPUOFF\tGIE\tN\tZ\tC",
// ),
// Re::cg => println!("cg (r3) is the Constant Generator. It's hard-wired to zero."),
// Re::r4 | Re::r5 | Re::r6 | Re::r7 | Re::r8 | Re::r9 | Re::r10 | Re::r11 => {
// println!("{r} is a callee-saved general purpose register.")
// }
// Re::r12 | Re::r13 | Re::r14 | Re::r15 => {
// println!("{r} is a caller-saved general purpose register, allowed for return values.")
// }
// }
// }
// }
pub fn usage(opcode: &Opcode) -> (&'static str, &'static str) {
match opcode {
// Single
Opcode::Rrc => ("Rotates dst right, through carry flag", "dst = (dst >> 1) | (sr[C] << 15)"),
Opcode::Swpb => ("Swaps the high and low byte of dst", "dst.swap_bytes()"),
Opcode::Rra => ("Shifts dst right, sign-extending the result", "dst >>= 1"),
Opcode::Sxt => ("Sign-extends the 8-bit dst to 16-bits", "dst as i16 << 8 >> 8"),
Opcode::Push => ("Pushes dst to the stack", "stack.push(dst)"),
Opcode::Call => ("Calls a subroutine at an absolute address", "dst()"),
Opcode::Reti => ("Return from interrupt handler", "{ sr = stack.pop(); pc = stack.pop() }"),
// Jump
Opcode::Jnz => ("Jump if the last result was not zero", "if !Z { pc += target }"),
Opcode::Jz => ("Jump if the last result was zero", "if Z { pc += target }"),
Opcode::Jnc => ("Jump if the last operation did not carry", "if !C { pc += target }"),
Opcode::Jc => ("Jump if the last operation produced a carry bit", "if C { pc += target }"),
Opcode::Jn => ("Jump if the last result was negative", "if N { pc += target }"),
Opcode::Jge => ("Jump if the flags indicate src >= dst", "if sr[C] == sr[V] { pc += target }"),
Opcode::Jl => ("Jump if the flags indicate src < dst", "if sr[C] != sr[V] { pc += target }"),
Opcode::Jmp => ("Jump unconditionally", "pc += target"),
// Double
Opcode::Mov => ("Copy src into dst", "dst = src"),
Opcode::Add => ("Add src to dst", "dst += src"),
Opcode::Addc => ("Add src to dst with carry", "dst += src + sr[C]"),
Opcode::Subc => ("Subtract src from dst with carry", "dst -= src - sr[C]"),
Opcode::Sub => ("Subtract src from dst", "dst -= src"),
Opcode::Cmp => ("Subtract src from dst, but discard the result, keeping the flags", "dst - src"),
Opcode::Dadd => ("Add src to dst in Binary Coded Decimal", "dst = dst as BCD + src as BCD"),
Opcode::Bit => ("Test if bits in src are set in dst", "(src & dst).cmp(0)"),
Opcode::Bic => ("Clear bits in dst that are set in src, without changing flags", "dst &= !src"),
Opcode::Bis => ("Set bits in dst that are set in src, without changing flags", "dst |= src"),
Opcode::Xor => ("Bitwise Xor src into dst", "dst ^= src"),
Opcode::And => ("Bitwise And src into dst", "dst &= src"),
// Emulated
Opcode::Nop => ("Does nothing", "{}"),
Opcode::Pop => ("Pops a value from the stack", "dst = stack.pop()"),
Opcode::Br => ("Branches to the absolute address in src", "pc = src"),
Opcode::Ret => ("Returns from subroutine", "pc = stack.pop()"),
Opcode::Clrc => ("Clears the carry flag", "sr[C] = 0"),
Opcode::Setc => ("Sets the carry flag", "sr[C] = 1"),
Opcode::Clrz => ("Clears the zero flag", "sr[Z] = 0"),
Opcode::Setz => ("Sets the zero flag", "sr[Z] = 1"),
Opcode::Clrn => ("Clears the negative flag", "sr[N] = 0"),
Opcode::Setn => ("Sets the negative flag", "sr[N] = 1"),
Opcode::Dint => ("Disables interrupts", "sr[GIE] = 0"),
Opcode::Eint => ("Enables interrupts", "sr[GIE] = 1"),
Opcode::Rla => ("Shifts dst to the left, padding with zeros", "dst <<= 1"),
Opcode::Rlc => ("Rotates dst to the left, through carry flag", "dst = (dst << 1) + sr[C]"),
Opcode::Inv => ("Inverts the bits in dst", "dst = !dst"),
Opcode::Clr => ("Sets dst to 0", "dst = 0"),
Opcode::Tst => ("Sets the status register flags (CNZV) using dst", ""),
Opcode::Dec => ("Decrements dst", "dst -= 1"),
Opcode::Decd => ("Decrements dst by 2 (one processor word)", "dst -= 2"),
Opcode::Inc => ("Increments dst", "dst += 1"),
Opcode::Incd => ("Increments dst by 2 (one processor word)", "dst += 2"),
Opcode::Adc => ("Adds the carry bit to dst", "dst += sr[C]"),
Opcode::Dadc => ("Adds the carry bit to dst, in Binary Coded Decimal", "dst as BCD = sr[C]"),
Opcode::Sbc => ("Subtracts the carry bit from dst", "dst -= sr[C]"),
}
}
// // Gets parameter usage information from the opcode's EncodingParser
// pub fn params(opcode: &Opcode) -> &'static str {
// match opcode.resolve().1 {
// EncodingParser::Jump { target: None } => " target (relative address or label)",
// EncodingParser::Single { width: None, dst: None } => "[.b] dst",
// EncodingParser::Single { dst: None, .. } => " dst",
// EncodingParser::Double { src: None, dst: None, .. } => "[.b] src, dst",
// EncodingParser::Double { src: None, .. } => "[.b] src",
// EncodingParser::Double { dst: None, .. } => "[.b] dst",
// EncodingParser::Double { .. } => "[.b]",
// EncodingParser::Reflexive { reg: None, .. } => "[.b] dst",
// _ => "",
// }
// }
const SINGLE: [Opcode; 7] =
[Opcode::Rrc, Opcode::Swpb, Opcode::Rra, Opcode::Sxt, Opcode::Push, Opcode::Call, Opcode::Reti];
// pub fn usage(opcode: &Opcode) -> (&'static str, &'static str) {
// match opcode {
// // Single
// Opcode::Rrc => ("Rotates dst right, through carry flag", "dst = (dst >> 1) | (sr[C] << 15)"),
// Opcode::Swpb => ("Swaps the high and low byte of dst", "dst.swap_bytes()"),
// Opcode::Rra => ("Shifts dst right, sign-extending the result", "dst >>= 1"),
// Opcode::Sxt => ("Sign-extends the 8-bit dst to 16-bits", "dst as i16 << 8 >> 8"),
// Opcode::Push => ("Pushes dst to the stack", "stack.push(dst)"),
// Opcode::Call => ("Calls a subroutine at an absolute address", "dst()"),
// Opcode::Reti => ("Return from interrupt handler", "{ sr = stack.pop(); pc = stack.pop() }"),
// // Jump
// Opcode::Jnz => ("Jump if the last result was not zero", "if !Z { pc += target }"),
// Opcode::Jz => ("Jump if the last result was zero", "if Z { pc += target }"),
// Opcode::Jnc => ("Jump if the last operation did not carry", "if !C { pc += target }"),
// Opcode::Jc => ("Jump if the last operation produced a carry bit", "if C { pc += target }"),
// Opcode::Jn => ("Jump if the last result was negative", "if N { pc += target }"),
// Opcode::Jge => ("Jump if the flags indicate src >= dst", "if sr[C] == sr[V] { pc += target }"),
// Opcode::Jl => ("Jump if the flags indicate src < dst", "if sr[C] != sr[V] { pc += target }"),
// Opcode::Jmp => ("Jump unconditionally", "pc += target"),
// // Double
// Opcode::Mov => ("Copy src into dst", "dst = src"),
// Opcode::Add => ("Add src to dst", "dst += src"),
// Opcode::Addc => ("Add src to dst with carry", "dst += src + sr[C]"),
// Opcode::Subc => ("Subtract src from dst with carry", "dst -= src - sr[C]"),
// Opcode::Sub => ("Subtract src from dst", "dst -= src"),
// Opcode::Cmp => ("Subtract src from dst, but discard the result, keeping the flags", "dst - src"),
// Opcode::Dadd => ("Add src to dst in Binary Coded Decimal", "dst = dst as BCD + src as BCD"),
// Opcode::Bit => ("Test if bits in src are set in dst", "(src & dst).cmp(0)"),
// Opcode::Bic => ("Clear bits in dst that are set in src, without changing flags", "dst &= !src"),
// Opcode::Bis => ("Set bits in dst that are set in src, without changing flags", "dst |= src"),
// Opcode::Xor => ("Bitwise Xor src into dst", "dst ^= src"),
// Opcode::And => ("Bitwise And src into dst", "dst &= src"),
// // Emulated
// Opcode::Nop => ("Does nothing", "{}"),
// Opcode::Pop => ("Pops a value from the stack", "dst = stack.pop()"),
// Opcode::Br => ("Branches to the absolute address in src", "pc = src"),
// Opcode::Ret => ("Returns from subroutine", "pc = stack.pop()"),
// Opcode::Clrc => ("Clears the carry flag", "sr[C] = 0"),
// Opcode::Setc => ("Sets the carry flag", "sr[C] = 1"),
// Opcode::Clrz => ("Clears the zero flag", "sr[Z] = 0"),
// Opcode::Setz => ("Sets the zero flag", "sr[Z] = 1"),
// Opcode::Clrn => ("Clears the negative flag", "sr[N] = 0"),
// Opcode::Setn => ("Sets the negative flag", "sr[N] = 1"),
// Opcode::Dint => ("Disables interrupts", "sr[GIE] = 0"),
// Opcode::Eint => ("Enables interrupts", "sr[GIE] = 1"),
// Opcode::Rla => ("Shifts dst to the left, padding with zeros", "dst <<= 1"),
// Opcode::Rlc => ("Rotates dst to the left, through carry flag", "dst = (dst << 1) + sr[C]"),
// Opcode::Inv => ("Inverts the bits in dst", "dst = !dst"),
// Opcode::Clr => ("Sets dst to 0", "dst = 0"),
// Opcode::Tst => ("Sets the status register flags (CNZV) using dst", ""),
// Opcode::Dec => ("Decrements dst", "dst -= 1"),
// Opcode::Decd => ("Decrements dst by 2 (one processor word)", "dst -= 2"),
// Opcode::Inc => ("Increments dst", "dst += 1"),
// Opcode::Incd => ("Increments dst by 2 (one processor word)", "dst += 2"),
// Opcode::Adc => ("Adds the carry bit to dst", "dst += sr[C]"),
// Opcode::Dadc => ("Adds the carry bit to dst, in Binary Coded Decimal", "dst as BCD = sr[C]"),
// Opcode::Sbc => ("Subtracts the carry bit from dst", "dst -= sr[C]"),
// }
// }
const JUMP: [Opcode; 8] =
[Opcode::Jnz, Opcode::Jz, Opcode::Jnc, Opcode::Jc, Opcode::Jn, Opcode::Jge, Opcode::Jl, Opcode::Jmp];
// const SINGLE: [Opcode; 7] =
// [Opcode::Rrc, Opcode::Swpb, Opcode::Rra, Opcode::Sxt, Opcode::Push, Opcode::Call, Opcode::Reti];
#[rustfmt::skip]
const DOUBLE: [Opcode; 12] = [
Opcode::Mov, Opcode::Add, Opcode::Addc, Opcode::Subc, Opcode::Sub, Opcode::Cmp,
Opcode::Dadd, Opcode::Bit, Opcode::Bic, Opcode::Bis, Opcode::Xor, Opcode::And,
];
#[rustfmt::skip]
const SIMULATED: [Opcode; 24] = [
Opcode::Nop, Opcode::Pop, Opcode::Br, Opcode::Ret, Opcode::Clrc, Opcode::Setc,
Opcode::Clrz, Opcode::Setz, Opcode::Clrn, Opcode::Setn, Opcode::Dint, Opcode::Eint,
Opcode::Rla, Opcode::Rlc, Opcode::Inv, Opcode::Clr, Opcode::Tst, Opcode::Dec,
Opcode::Decd, Opcode::Inc, Opcode::Incd, Opcode::Adc, Opcode::Dadc, Opcode::Sbc,
];
// const JUMP: [Opcode; 8] =
// [Opcode::Jnz, Opcode::Jz, Opcode::Jnc, Opcode::Jc, Opcode::Jn, Opcode::Jge, Opcode::Jl, Opcode::Jmp];
pub fn list_opcodes() {
let mut stdout = std::io::stdout().lock();
header!(stdout, "Single-operand instructions:");
let _ = write_opcode_list(&mut stdout, &SINGLE);
header!(stdout, "Relative Jump instructions:");
let _ = write_opcode_list(&mut stdout, &JUMP);
header!(stdout, "Double-operand instructions:");
let _ = write_opcode_list(&mut stdout, &DOUBLE);
header!(stdout, "Simulated instructions:");
let _ = write_opcode_list(&mut stdout, &SIMULATED);
}
// #[rustfmt::skip]
// const DOUBLE: [Opcode; 12] = [
// Opcode::Mov, Opcode::Add, Opcode::Addc, Opcode::Subc, Opcode::Sub, Opcode::Cmp,
// Opcode::Dadd, Opcode::Bit, Opcode::Bic, Opcode::Bis, Opcode::Xor, Opcode::And,
// ];
// #[rustfmt::skip]
// const SIMULATED: [Opcode; 24] = [
// Opcode::Nop, Opcode::Pop, Opcode::Br, Opcode::Ret, Opcode::Clrc, Opcode::Setc,
// Opcode::Clrz, Opcode::Setz, Opcode::Clrn, Opcode::Setn, Opcode::Dint, Opcode::Eint,
// Opcode::Rla, Opcode::Rlc, Opcode::Inv, Opcode::Clr, Opcode::Tst, Opcode::Dec,
// Opcode::Decd, Opcode::Inc, Opcode::Incd, Opcode::Adc, Opcode::Dadc, Opcode::Sbc,
// ];
fn write_opcode_list(mut f: impl std::io::Write, list: &[Opcode]) -> std::io::Result<()> {
for (idx, opcode) in list.iter().enumerate() {
write!(f, "{opcode}{}", if idx % 6 == 5 { "\n" } else { "\t" })?;
}
if list.len() % 6 != 0 {
writeln!(f)?;
}
Ok(())
}
// pub fn list_opcodes() {
// let mut stdout = std::io::stdout().lock();
// header!(stdout, "Single-operand instructions:");
// let _ = write_opcode_list(&mut stdout, &SINGLE);
// header!(stdout, "Relative Jump instructions:");
// let _ = write_opcode_list(&mut stdout, &JUMP);
// header!(stdout, "Double-operand instructions:");
// let _ = write_opcode_list(&mut stdout, &DOUBLE);
// header!(stdout, "Simulated instructions:");
// let _ = write_opcode_list(&mut stdout, &SIMULATED);
// }
macro header ($f:ident, $($x: expr),+) {
{write!($f, "{}",SetForegroundColor(Color::Cyan)).ok();write!($f, $($x),+).ok();writeln!($f, "{}",ResetAttributes).ok();}
}
macro footer ($($x: expr),+) {
{print!("{}",SetForegroundColor(Color::DarkGray));print!($($x),+);println!("{}",ResetAttributes);}
}
// fn write_opcode_list(mut f: impl std::io::Write, list: &[Opcode]) -> std::io::Result<()> {
// for (idx, opcode) in list.iter().enumerate() {
// write!(f, "{opcode}{}", if idx % 6 == 5 { "\n" } else { "\t" })?;
// }
// if list.len() % 6 != 0 {
// writeln!(f)?;
// }
// Ok(())
// }
// macro header ($f:ident, $($x: expr),+) {
// {write!($f, "{}",SetForegroundColor(Color::Cyan)).ok();write!($f, $($x),+).ok();writeln!($f, "{}",ResetAttributes).ok();}
// }
// macro footer ($($x: expr),+) {
// {print!("{}",SetForegroundColor(Color::DarkGray));print!($($x),+);println!("{}",ResetAttributes);}
// }

View File

@@ -3,59 +3,63 @@
// https://mspgcc.sourceforge.net/manual/ln16.html
#![feature(decl_macro)]
use anes::{Color, ResetAttributes, SetForegroundColor};
use msp430_asm::parser::preamble::*;
use msp430_asm::preamble::*;
use std::{
error::Error,
io::{stdin, IsTerminal, Write},
};
type AsmResult<T> = Result<T, Box<dyn Error>>;
mod data;
fn main() -> AsmResult<()> {
if stdin().is_terminal() {
hello();
}
repl()
fn main() {
println!("Hello, world!")
}
fn hello() {
println!(
"{}{} v{}
This software contains instruction and register descriptions adapted from
the mspgcc project's fantastic documentation, which is licensed under the GPL.
https://mspgcc.sourceforge.net/manual/book1.html{}\n",
SetForegroundColor(Color::DarkGray),
env!("CARGO_BIN_NAME"),
env!("CARGO_PKG_VERSION"),
ResetAttributes
);
}
// use anes::{Color, ResetAttributes, SetForegroundColor};
// use msp430_asm::parser::preamble::*;
// use msp430_asm::preamble::*;
// use std::{
// error::Error,
// io::{stdin, IsTerminal, Write},
// };
fn repl() -> AsmResult<()> {
printflush!("> ");
let mut line = String::new();
while let Ok(len) = stdin().read_line(&mut line) {
match len {
0 => break, // No newline (reached EOF)
1 => (), // Line is empty
_ => {
if line.starts_with('?') || line.starts_with("help") {
data::list_opcodes()
} else if let Ok(sf) = data::SyntaxFragment::try_from(line.as_str()) {
sf.info();
}
}
}
printflush!("> ");
line.clear();
}
Ok(())
}
// type AsmResult<T> = Result<T, Box<dyn Error>>;
macro printflush ($($x: expr),+) {
{print!($($x),+); let _ = ::std::io::stdout().flush();}
}
// mod data;
// fn main() -> AsmResult<()> {
// if stdin().is_terminal() {
// hello();
// }
// repl()
// }
// fn hello() {
// println!(
// "{}{} v{}
// This software contains instruction and register descriptions adapted from
// the mspgcc project's fantastic documentation, which is licensed under the GPL.
// https://mspgcc.sourceforge.net/manual/book1.html{}\n",
// SetForegroundColor(Color::DarkGray),
// env!("CARGO_BIN_NAME"),
// env!("CARGO_PKG_VERSION"),
// ResetAttributes
// );
// }
// fn repl() -> AsmResult<()> {
// printflush!("> ");
// let mut line = String::new();
// while let Ok(len) = stdin().read_line(&mut line) {
// match len {
// 0 => break, // No newline (reached EOF)
// 1 => (), // Line is empty
// _ => {
// if line.starts_with('?') || line.starts_with("help") {
// data::list_opcodes()
// } else if let Ok(sf) = data::SyntaxFragment::try_from(line.as_str()) {
// sf.info();
// }
// }
// }
// printflush!("> ");
// line.clear();
// }
// Ok(())
// }
// macro printflush ($($x: expr),+) {
// {print!($($x),+); let _ = ::std::io::stdout().flush();}
// }