John Breaux
fbc0a0b2ea
- Improved test coverage to >80% of lines, functions
- When doctests are included.
- Wrote new unit tests:
- Explicit tests for invalid instructions in the
ranges {`5xyn`, `8xyn`, `9xyn`, `Fxbb`}
- `rand` Tests for 1052671 cycles, to ensure
randomly generated number is < ANDed byte
- `Ex9E` (sek), `ExA1`(snek) will press only the expected key,
then every key except the expected key, for every address
- `Fx0A` (waitk) asserts based on the waveform of a keypress.
After all, an A press is an A press.
- Improved test performance by printing slightly less
- Removed nightly requirement
- (now optional, with feature = "unstable")
- Amended justfile to test with `cargo nextest` (nice)
- Changed release builds to optlevel 3
1128 lines
34 KiB
Rust
1128 lines
34 KiB
Rust
// (c) 2023 John A. Breaux
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// This code is licensed under MIT license (see LICENSE.txt for details)
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//! Decodes and runs instructions
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#[cfg(test)]
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mod tests;
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pub mod disassemble;
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use self::disassemble::Disassemble;
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use crate::bus::{Bus, Read, Region, Write};
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use owo_colors::OwoColorize;
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use rand::random;
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use std::time::Instant;
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type Reg = usize;
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type Adr = u16;
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type Nib = u8;
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/// Controls the authenticity behavior of the CPU on a granular level.
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#[derive(Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct Quirks {
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/// Binary ops in `8xy`(`1`, `2`, `3`) should set vF to 0
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pub bin_ops: bool,
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/// Shift ops in `8xy`(`6`, `E`) should source from vY instead of vX
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pub shift: bool,
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/// Draw operations should pause execution until the next timer tick
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pub draw_wait: bool,
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/// DMA instructions `Fx55`/`Fx65` should change I to I + x + 1
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pub dma_inc: bool,
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/// Indexed jump instructions should go to ADR + v`N` where `N` is high nibble of adr
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pub stupid_jumps: bool,
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}
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impl From<bool> for Quirks {
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fn from(value: bool) -> Self {
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if value {
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Quirks {
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bin_ops: true,
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shift: true,
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draw_wait: true,
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dma_inc: true,
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stupid_jumps: false,
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}
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} else {
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Quirks {
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bin_ops: false,
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shift: false,
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draw_wait: false,
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dma_inc: false,
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stupid_jumps: false,
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}
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}
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}
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}
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impl Default for Quirks {
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fn default() -> Self {
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Self::from(false)
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}
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}
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#[derive(Clone, Debug, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct ControlFlags {
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pub debug: bool,
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pub pause: bool,
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pub keypause: bool,
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pub vbi_wait: bool,
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pub lastkey: Option<usize>,
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pub quirks: Quirks,
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pub monotonic: Option<usize>,
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}
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impl ControlFlags {
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/// Toggles debug mode
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///
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// assert_eq!(true, cpu.flags.debug);
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/// cpu.flags.debug();
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/// assert_eq!(false, cpu.flags.debug);
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///# Ok(())
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///# }
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/// ```
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pub fn debug(&mut self) {
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self.debug = !self.debug
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}
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/// Toggles pause
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///
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// assert_eq!(false, cpu.flags.pause);
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/// cpu.flags.pause();
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/// assert_eq!(true, cpu.flags.pause);
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///# Ok(())
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///# }
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/// ```
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pub fn pause(&mut self) {
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self.pause = !self.pause
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}
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}
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/// Represents the internal state of the CPU interpreter
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#[derive(Clone, Debug, PartialEq)]
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pub struct CPU {
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pub flags: ControlFlags,
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// memory map info
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screen: Adr,
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font: Adr,
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// registers
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pc: Adr,
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sp: Adr,
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i: Adr,
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v: [u8; 16],
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delay: f64,
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sound: f64,
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// I/O
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keys: [bool; 16],
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// Execution data
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timer: Instant,
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cycle: usize,
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breakpoints: Vec<Adr>,
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disassembler: Disassemble,
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}
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// public interface
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impl CPU {
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// TODO: implement From<&bus> for CPU
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/// Constructs a new CPU, taking all configurable parameters
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/// # Examples
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/// ```rust
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/// # use chirp::prelude::*;
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/// let cpu = CPU::new(
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/// 0xf00, // screen location
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/// 0x50, // font location
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/// 0x200, // start of program
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/// 0xefe, // top of stack
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/// Disassemble::default(),
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/// vec![], // Breakpoints
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/// ControlFlags::default()
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/// );
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/// dbg!(cpu);
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/// ```
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pub fn new(
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screen: Adr,
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font: Adr,
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pc: Adr,
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sp: Adr,
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disassembler: Disassemble,
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breakpoints: Vec<Adr>,
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flags: ControlFlags,
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) -> Self {
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CPU {
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disassembler,
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screen,
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font,
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pc,
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sp,
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breakpoints,
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flags,
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..Default::default()
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}
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}
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/// Presses a key
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// cpu.press(0x7);
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/// cpu.press(0xF);
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///# Ok(())
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///# }
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/// ```
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pub fn press(&mut self, key: usize) {
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if (0..16).contains(&key) {
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self.keys[key] = true;
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}
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}
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/// Releases a key
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///
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/// If keypause is enabled, this disables keypause and records the last released key.
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// cpu.press(0x7);
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/// cpu.release(0x7);
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///# Ok(())
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///# }
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/// ```
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pub fn release(&mut self, key: usize) {
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if (0..16).contains(&key) {
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self.keys[key] = false;
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if self.flags.keypause {
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self.flags.lastkey = Some(key);
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}
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self.flags.keypause = false;
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}
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}
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/// Sets a general purpose register in the CPU
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/// # Examples
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/// ```rust
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/// # use chirp::prelude::*;
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/// // Create a new CPU, and set v4 to 0x41
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/// let mut cpu = CPU::default();
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/// cpu.set_gpr(0x4, 0x41);
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/// // Dump the CPU registers
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/// cpu.dump();
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/// ```
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pub fn set_gpr(&mut self, gpr: Reg, value: u8) {
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if let Some(gpr) = self.v.get_mut(gpr) {
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*gpr = value;
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}
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}
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/// Gets the program counter
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// assert_eq!(0x200, cpu.pc());
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///# Ok(())
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///# }
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/// ```
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pub fn pc(&self) -> Adr {
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self.pc
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}
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/// Gets the number of cycles the CPU has executed
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///
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/// If cpu.flags.monotonic is Some, the cycle count will be
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/// updated even when the CPU is in drawpause or keypause
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// assert_eq!(0x0, cpu.cycle());
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///# Ok(())
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///# }
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/// ```
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pub fn cycle(&self) -> usize {
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self.cycle
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}
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/// Soft resets the CPU, releasing keypause and
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/// reinitializing the program counter to 0x200
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::new(
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/// 0xf00,
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/// 0x50,
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/// 0x340,
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/// 0xefe,
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/// Disassemble::default(),
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/// vec![],
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/// ControlFlags::default()
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/// );
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/// cpu.flags.keypause = true;
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/// cpu.flags.vbi_wait = true;
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/// assert_eq!(0x340, cpu.pc());
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/// cpu.soft_reset();
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/// assert_eq!(0x200, cpu.pc());
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/// assert_eq!(false, cpu.flags.keypause);
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/// assert_eq!(false, cpu.flags.vbi_wait);
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///# Ok(())
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///# }
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/// ```
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pub fn soft_reset(&mut self) {
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self.pc = 0x200;
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self.flags.keypause = false;
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self.flags.vbi_wait = false;
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}
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/// Set a breakpoint
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// TODO: Unit test this
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pub fn set_break(&mut self, point: Adr) -> &mut Self {
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if !self.breakpoints.contains(&point) {
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self.breakpoints.push(point)
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}
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self
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}
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/// Unset a breakpoint
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// TODO: Unit test this
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pub fn unset_break(&mut self, point: Adr) -> &mut Self {
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fn linear_find(needle: Adr, haystack: &Vec<Adr>) -> Option<usize> {
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for (i, v) in haystack.iter().enumerate() {
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if *v == needle {
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return Some(i);
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}
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}
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None
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}
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if let Some(idx) = linear_find(point, &self.breakpoints) {
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assert_eq!(point, self.breakpoints.swap_remove(idx));
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}
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self
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}
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/// Unpauses the emulator for a single tick,
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/// even if cpu.flags.pause is set.
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///
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/// NOTE: does not synchronize with delay timers
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// let mut bus = bus!{
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/// Program [0x0200..0x0f00] = &[
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/// 0x00, 0xe0, // cls
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/// 0x22, 0x02, // jump 0x202 (pc)
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/// ],
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/// Screen [0x0f00..0x1000],
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/// };
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/// cpu.singlestep(&mut bus);
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/// assert_eq!(0x202, cpu.pc());
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/// assert_eq!(1, cpu.cycle());
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///# Ok(())
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///# }
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/// ```
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pub fn singlestep(&mut self, bus: &mut Bus) -> &mut Self {
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self.flags.pause = false;
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self.tick(bus);
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self.flags.vbi_wait = false;
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self.flags.pause = true;
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self
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}
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/// Unpauses the emulator for `steps` ticks
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///
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/// Ticks the timers every `rate` ticks
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// let mut bus = bus!{
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/// Program [0x0200..0x0f00] = &[
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/// 0x00, 0xe0, // cls
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/// 0x22, 0x02, // jump 0x202 (pc)
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/// ],
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/// Screen [0x0f00..0x1000],
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/// };
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/// cpu.multistep(&mut bus, 0x20);
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/// assert_eq!(0x202, cpu.pc());
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/// assert_eq!(0x20, cpu.cycle());
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///# Ok(())
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///# }
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/// ```
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pub fn multistep(&mut self, bus: &mut Bus, steps: usize) -> &mut Self {
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for _ in 0..steps {
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self.tick(bus);
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self.vertical_blank();
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}
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self
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}
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/// Simulates vertical blanking
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///
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/// If monotonic timing is `enabled`:
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/// - Ticks the sound and delay timers according to CPU cycle count
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/// - Disables framepause
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/// If monotonic timing is `disabled`:
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/// - Subtracts the elapsed time in fractions of a frame
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/// from st/dt
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/// - Disables framepause if the duration exceeds that of a frame
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pub fn vertical_blank(&mut self) -> &mut Self {
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if self.flags.pause {
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return self;
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}
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// Use a monotonic counter when testing
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if let Some(speed) = self.flags.monotonic {
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if self.flags.vbi_wait {
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self.flags.vbi_wait = !(self.cycle % speed == 0);
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}
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self.delay -= 1.0 / speed as f64;
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self.sound -= 1.0 / speed as f64;
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return self;
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};
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let time = self.timer.elapsed().as_secs_f64() * 60.0;
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self.timer = Instant::now();
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if time > 1.0 {
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self.flags.vbi_wait = false;
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}
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if self.delay > 0.0 {
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self.delay -= time;
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}
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if self.sound > 0.0 {
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self.sound -= time;
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}
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self
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}
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/// Executes a single instruction
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/// # Examples
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/// ```rust
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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/// let mut bus = bus!{
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/// Program [0x0200..0x0f00] = &[
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/// 0x00, 0xe0, // cls
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/// 0x22, 0x02, // jump 0x202 (pc)
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/// ],
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/// Screen [0x0f00..0x1000],
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/// };
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/// cpu.tick(&mut bus);
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/// assert_eq!(0x202, cpu.pc());
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/// assert_eq!(1, cpu.cycle());
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///# Ok(())
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///# }
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/// ```
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/// # Panics
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/// Will panic if an invalid instruction is executed
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/// ```rust,should_panic
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///# use chirp::prelude::*;
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///# fn main() -> Result<()> {
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/// let mut cpu = CPU::default();
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///# cpu.flags.debug = true; // enable live disassembly
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///# cpu.flags.monotonic = Some(8); // enable monotonic/test timing
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/// let mut bus = bus!{
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/// Program [0x0200..0x0f00] = &[
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/// 0xff, 0xff, // invalid!
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/// 0x22, 0x02, // jump 0x202 (pc)
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/// ],
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/// Screen [0x0f00..0x1000],
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/// };
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/// cpu.multistep(&mut bus, 0x10); // panics!
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///# Ok(())
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///# }
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/// ```
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pub fn tick(&mut self, bus: &mut Bus) -> &mut Self {
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// Do nothing if paused
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if self.flags.pause || self.flags.vbi_wait || self.flags.keypause {
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// always tick in test mode
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if self.flags.monotonic.is_some() {
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self.cycle += 1;
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}
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return self;
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}
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self.cycle += 1;
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// fetch opcode
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let opcode: u16 = bus.read(self.pc);
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let pc = self.pc;
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// DINC pc
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self.pc = self.pc.wrapping_add(2);
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// decode opcode
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use disassemble::{a, b, i, n, x, y};
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let (i, x, y, n, b, a) = (
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i(opcode),
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x(opcode),
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y(opcode),
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n(opcode),
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b(opcode),
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a(opcode),
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);
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match i {
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// # Issue a system call
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// |opcode| effect |
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// |------|------------------------------------|
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// | 00e0 | Clear screen memory to all 0 |
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// | 00ee | Return from subroutine |
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0x0 => match a {
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0x0e0 => self.clear_screen(bus),
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0x0ee => self.ret(bus),
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_ => self.sys(a),
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},
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// | 1aaa | Sets pc to an absolute address
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0x1 => self.jump(a),
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// | 2aaa | Pushes pc onto the stack, then jumps to a
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0x2 => self.call(a, bus),
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// | 3xbb | Skips next instruction if register X == b
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0x3 => self.skip_equals_immediate(x, b),
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// | 4xbb | Skips next instruction if register X != b
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0x4 => self.skip_not_equals_immediate(x, b),
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// # Performs a register-register comparison
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// |opcode| effect |
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// |------|------------------------------------|
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// | 9XY0 | Skip next instruction if vX == vY |
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0x5 => match n {
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0x0 => self.skip_equals(x, y),
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_ => self.unimplemented(opcode),
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},
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// 6xbb: Loads immediate byte b into register vX
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0x6 => self.load_immediate(x, b),
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// 7xbb: Adds immediate byte b to register vX
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0x7 => self.add_immediate(x, b),
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// # Performs ALU operation
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// |opcode| effect |
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// |------|------------------------------------|
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// | 8xy0 | Y = X |
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// | 8xy1 | X = X | Y |
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// | 8xy2 | X = X & Y |
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// | 8xy3 | X = X ^ Y |
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// | 8xy4 | X = X + Y; Set vF=carry |
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// | 8xy5 | X = X - Y; Set vF=carry |
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// | 8xy6 | X = X >> 1 |
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// | 8xy7 | X = Y - X; Set vF=carry |
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// | 8xyE | X = X << 1 |
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|
0x8 => match n {
|
|
0x0 => self.load(x, y),
|
|
0x1 => self.or(x, y),
|
|
0x2 => self.and(x, y),
|
|
0x3 => self.xor(x, y),
|
|
0x4 => self.add(x, y),
|
|
0x5 => self.sub(x, y),
|
|
0x6 => self.shift_right(x, y),
|
|
0x7 => self.backwards_sub(x, y),
|
|
0xE => self.shift_left(x, y),
|
|
_ => self.unimplemented(opcode),
|
|
},
|
|
// # Performs a register-register comparison
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | 9XY0 | Skip next instruction if vX != vY |
|
|
0x9 => match n {
|
|
0 => self.skip_not_equals(x, y),
|
|
_ => self.unimplemented(opcode),
|
|
},
|
|
// Aaaa: Load address #a into register I
|
|
0xa => self.load_i_immediate(a),
|
|
// Baaa: Jump to &adr + v0
|
|
0xb => self.jump_indexed(a),
|
|
// Cxbb: Stores a random number + the provided byte into vX
|
|
0xc => self.rand(x, b),
|
|
// Dxyn: Draws n-byte sprite to the screen at coordinates (vX, vY)
|
|
0xd => self.draw(x, y, n, bus),
|
|
|
|
// # Skips instruction on value of keypress
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | eX9e | Skip next instruction if key == vX |
|
|
// | eXa1 | Skip next instruction if key != vX |
|
|
0xe => match b {
|
|
0x9e => self.skip_key_equals(x),
|
|
0xa1 => self.skip_key_not_equals(x),
|
|
_ => self.unimplemented(opcode),
|
|
},
|
|
|
|
// # Performs IO
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | fX07 | Set vX to value in delay timer |
|
|
// | fX0a | Wait for input, store in vX m |
|
|
// | fX15 | Set sound timer to the value in vX |
|
|
// | fX18 | set delay timer to the value in vX |
|
|
// | fX1e | Add x to I |
|
|
// | fX29 | Load sprite for character x into I |
|
|
// | fX33 | BCD convert X into I[0..3] |
|
|
// | fX55 | DMA Stor from I to registers 0..X |
|
|
// | fX65 | DMA Load from I to registers 0..X |
|
|
0xf => match b {
|
|
0x07 => self.load_delay_timer(x),
|
|
0x0A => self.wait_for_key(x),
|
|
0x15 => self.store_delay_timer(x),
|
|
0x18 => self.store_sound_timer(x),
|
|
0x1E => self.add_i(x),
|
|
0x29 => self.load_sprite(x),
|
|
0x33 => self.bcd_convert(x, bus),
|
|
0x55 => self.store_dma(x, bus),
|
|
0x65 => self.load_dma(x, bus),
|
|
_ => self.unimplemented(opcode),
|
|
},
|
|
_ => unreachable!("Extracted nibble from byte, got >nibble?"),
|
|
}
|
|
let elapsed = self.timer.elapsed();
|
|
// Print opcode disassembly:
|
|
if self.flags.debug {
|
|
std::println!(
|
|
"{:3} {:03x}: {:<36}{:?}",
|
|
self.cycle.bright_black(),
|
|
pc,
|
|
self.disassembler.instruction(opcode),
|
|
elapsed.dimmed()
|
|
);
|
|
}
|
|
// process breakpoints
|
|
if self.breakpoints.contains(&self.pc) {
|
|
self.flags.pause = true;
|
|
}
|
|
self
|
|
}
|
|
|
|
/// Dumps the current state of all CPU registers, and the cycle count
|
|
/// # Examples
|
|
/// ```rust
|
|
///# use chirp::prelude::*;
|
|
///# fn main() -> Result<()> {
|
|
/// let mut cpu = CPU::default();
|
|
/// cpu.dump();
|
|
///# Ok(())
|
|
///# }
|
|
/// ```
|
|
/// outputs
|
|
/// ```text
|
|
/// PC: 0200, SP: 0efe, I: 0000
|
|
/// v0: 00 v1: 00 v2: 00 v3: 00
|
|
/// v4: 00 v5: 00 v6: 00 v7: 00
|
|
/// v8: 00 v9: 00 vA: 00 vB: 00
|
|
/// vC: 00 vD: 00 vE: 00 vF: 00
|
|
/// DLY: 0, SND: 0, CYC: 0
|
|
/// ```
|
|
pub fn dump(&self) {
|
|
//let dumpstyle = owo_colors::Style::new().bright_black();
|
|
std::println!(
|
|
"PC: {:04x}, SP: {:04x}, I: {:04x}\n{}DLY: {}, SND: {}, CYC: {:6}",
|
|
self.pc,
|
|
self.sp,
|
|
self.i,
|
|
self.v
|
|
.into_iter()
|
|
.enumerate()
|
|
.map(|(i, gpr)| {
|
|
format!(
|
|
"v{i:X}: {gpr:02x} {}",
|
|
match i % 4 {
|
|
3 => "\n",
|
|
_ => "",
|
|
}
|
|
)
|
|
})
|
|
.collect::<String>(),
|
|
self.delay,
|
|
self.sound,
|
|
self.cycle,
|
|
);
|
|
}
|
|
}
|
|
|
|
impl Default for CPU {
|
|
/// Constructs a new CPU with sane defaults and debug mode ON
|
|
///
|
|
/// | value | default | description
|
|
/// |--------|---------|------------
|
|
/// | screen |`0x0f00` | Location of screen memory.
|
|
/// | font |`0x0050` | Location of font memory.
|
|
/// | pc |`0x0200` | Start location. Generally 0x200 or 0x600.
|
|
/// | sp |`0x0efe` | Initial top of stack.
|
|
///
|
|
///
|
|
/// # Examples
|
|
/// ```rust
|
|
/// use chirp::prelude::*;
|
|
/// let mut cpu = CPU::default();
|
|
/// ```
|
|
fn default() -> Self {
|
|
CPU {
|
|
screen: 0xf00,
|
|
font: 0x050,
|
|
pc: 0x200,
|
|
sp: 0xefe,
|
|
i: 0,
|
|
v: [0; 16],
|
|
delay: 0.0,
|
|
sound: 0.0,
|
|
cycle: 0,
|
|
keys: [false; 16],
|
|
flags: ControlFlags {
|
|
debug: true,
|
|
..Default::default()
|
|
},
|
|
timer: Instant::now(),
|
|
breakpoints: vec![],
|
|
disassembler: Disassemble::default(),
|
|
}
|
|
}
|
|
}
|
|
|
|
// Below this point, comments may be duplicated per impl' block,
|
|
// since some opcodes handle multiple instructions.
|
|
|
|
// | 0aaa | Issues a "System call" (ML routine)
|
|
//
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | 00e0 | Clear screen memory to all 0 |
|
|
// | 00ee | Return from subroutine |
|
|
impl CPU {
|
|
/// Unused instructions
|
|
#[inline]
|
|
fn unimplemented(&self, opcode: u16) {
|
|
unimplemented!("Opcode: {opcode:04x}")
|
|
}
|
|
/// 0aaa: Handles a "machine language function call" (lmao)
|
|
#[inline]
|
|
fn sys(&mut self, a: Adr) {
|
|
unimplemented!("SYS\t{a:03x}");
|
|
}
|
|
/// 00e0: Clears the screen memory to 0
|
|
#[inline]
|
|
fn clear_screen(&mut self, bus: &mut Bus) {
|
|
if let Some(screen) = bus.get_region_mut(Region::Screen) {
|
|
for byte in screen {
|
|
*byte = 0;
|
|
}
|
|
}
|
|
}
|
|
/// 00ee: Returns from subroutine
|
|
#[inline]
|
|
fn ret(&mut self, bus: &impl Read<u16>) {
|
|
self.sp = self.sp.wrapping_add(2);
|
|
self.pc = bus.read(self.sp);
|
|
}
|
|
}
|
|
|
|
// | 1aaa | Sets pc to an absolute address
|
|
impl CPU {
|
|
/// 1aaa: Sets the program counter to an absolute address
|
|
#[inline]
|
|
fn jump(&mut self, a: Adr) {
|
|
// jump to self == halt
|
|
if a.wrapping_add(2) == self.pc {
|
|
self.flags.pause = true;
|
|
}
|
|
self.pc = a;
|
|
}
|
|
}
|
|
|
|
// | 2aaa | Pushes pc onto the stack, then jumps to a
|
|
impl CPU {
|
|
/// 2aaa: Pushes pc onto the stack, then jumps to a
|
|
#[inline]
|
|
fn call(&mut self, a: Adr, bus: &mut impl Write<u16>) {
|
|
bus.write(self.sp, self.pc);
|
|
self.sp = self.sp.wrapping_sub(2);
|
|
self.pc = a;
|
|
}
|
|
}
|
|
|
|
// | 3xbb | Skips next instruction if register X == b
|
|
impl CPU {
|
|
/// 3xbb: Skips the next instruction if register X == b
|
|
#[inline]
|
|
fn skip_equals_immediate(&mut self, x: Reg, b: u8) {
|
|
if self.v[x] == b {
|
|
self.pc = self.pc.wrapping_add(2);
|
|
}
|
|
}
|
|
}
|
|
|
|
// | 4xbb | Skips next instruction if register X != b
|
|
impl CPU {
|
|
/// 4xbb: Skips the next instruction if register X != b
|
|
#[inline]
|
|
fn skip_not_equals_immediate(&mut self, x: Reg, b: u8) {
|
|
if self.v[x] != b {
|
|
self.pc = self.pc.wrapping_add(2);
|
|
}
|
|
}
|
|
}
|
|
|
|
// | 5xyn | Performs a register-register comparison
|
|
//
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | 5XY0 | Skip next instruction if vX == vY |
|
|
impl CPU {
|
|
/// 5xy0: Skips the next instruction if register X != register Y
|
|
#[inline]
|
|
fn skip_equals(&mut self, x: Reg, y: Reg) {
|
|
if self.v[x] == self.v[y] {
|
|
self.pc = self.pc.wrapping_add(2);
|
|
}
|
|
}
|
|
}
|
|
|
|
// | 6xbb | Loads immediate byte b into register vX
|
|
impl CPU {
|
|
/// 6xbb: Loads immediate byte b into register vX
|
|
#[inline]
|
|
fn load_immediate(&mut self, x: Reg, b: u8) {
|
|
self.v[x] = b;
|
|
}
|
|
}
|
|
|
|
// | 7xbb | Adds immediate byte b to register vX
|
|
impl CPU {
|
|
/// 7xbb: Adds immediate byte b to register vX
|
|
#[inline]
|
|
fn add_immediate(&mut self, x: Reg, b: u8) {
|
|
self.v[x] = self.v[x].wrapping_add(b);
|
|
}
|
|
}
|
|
|
|
// | 8xyn | Performs ALU operation
|
|
//
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | 8xy0 | Y = X |
|
|
// | 8xy1 | X = X | Y |
|
|
// | 8xy2 | X = X & Y |
|
|
// | 8xy3 | X = X ^ Y |
|
|
// | 8xy4 | X = X + Y; Set vF=carry |
|
|
// | 8xy5 | X = X - Y; Set vF=carry |
|
|
// | 8xy6 | X = X >> 1 |
|
|
// | 8xy7 | X = Y - X; Set vF=carry |
|
|
// | 8xyE | X = X << 1 |
|
|
impl CPU {
|
|
/// 8xy0: Loads the value of y into x
|
|
#[inline]
|
|
fn load(&mut self, x: Reg, y: Reg) {
|
|
self.v[x] = self.v[y];
|
|
}
|
|
/// 8xy1: Performs bitwise or of vX and vY, and stores the result in vX
|
|
///
|
|
/// # Quirk
|
|
/// The original chip-8 interpreter will clobber vF for any 8-series instruction
|
|
#[inline]
|
|
fn or(&mut self, x: Reg, y: Reg) {
|
|
self.v[x] |= self.v[y];
|
|
if self.flags.quirks.bin_ops {
|
|
self.v[0xf] = 0;
|
|
}
|
|
}
|
|
/// 8xy2: Performs bitwise and of vX and vY, and stores the result in vX
|
|
///
|
|
/// # Quirk
|
|
/// The original chip-8 interpreter will clobber vF for any 8-series instruction
|
|
#[inline]
|
|
fn and(&mut self, x: Reg, y: Reg) {
|
|
self.v[x] &= self.v[y];
|
|
if self.flags.quirks.bin_ops {
|
|
self.v[0xf] = 0;
|
|
}
|
|
}
|
|
/// 8xy3: Performs bitwise xor of vX and vY, and stores the result in vX
|
|
///
|
|
/// # Quirk
|
|
/// The original chip-8 interpreter will clobber vF for any 8-series instruction
|
|
#[inline]
|
|
fn xor(&mut self, x: Reg, y: Reg) {
|
|
self.v[x] ^= self.v[y];
|
|
if self.flags.quirks.bin_ops {
|
|
self.v[0xf] = 0;
|
|
}
|
|
}
|
|
/// 8xy4: Performs addition of vX and vY, and stores the result in vX
|
|
#[inline]
|
|
fn add(&mut self, x: Reg, y: Reg) {
|
|
let carry;
|
|
(self.v[x], carry) = self.v[x].overflowing_add(self.v[y]);
|
|
self.v[0xf] = carry.into();
|
|
}
|
|
/// 8xy5: Performs subtraction of vX and vY, and stores the result in vX
|
|
#[inline]
|
|
fn sub(&mut self, x: Reg, y: Reg) {
|
|
let carry;
|
|
(self.v[x], carry) = self.v[x].overflowing_sub(self.v[y]);
|
|
self.v[0xf] = (!carry).into();
|
|
}
|
|
/// 8xy6: Performs bitwise right shift of vX
|
|
///
|
|
/// # Quirk
|
|
/// On the original chip-8 interpreter, this shifts vY and stores the result in vX
|
|
#[inline]
|
|
fn shift_right(&mut self, x: Reg, y: Reg) {
|
|
let src: Reg = if self.flags.quirks.shift { y } else { x };
|
|
let shift_out = self.v[src] & 1;
|
|
self.v[x] = self.v[src] >> 1;
|
|
self.v[0xf] = shift_out;
|
|
}
|
|
/// 8xy7: Performs subtraction of vY and vX, and stores the result in vX
|
|
#[inline]
|
|
fn backwards_sub(&mut self, x: Reg, y: Reg) {
|
|
let carry;
|
|
(self.v[x], carry) = self.v[y].overflowing_sub(self.v[x]);
|
|
self.v[0xf] = (!carry).into();
|
|
}
|
|
/// 8X_E: Performs bitwise left shift of vX
|
|
///
|
|
/// # Quirk
|
|
/// On the original chip-8 interpreter, this would perform the operation on vY
|
|
/// and store the result in vX. This behavior was left out, for now.
|
|
#[inline]
|
|
fn shift_left(&mut self, x: Reg, y: Reg) {
|
|
let src: Reg = if self.flags.quirks.shift { y } else { x };
|
|
let shift_out: u8 = self.v[src] >> 7;
|
|
self.v[x] = self.v[src] << 1;
|
|
self.v[0xf] = shift_out;
|
|
}
|
|
}
|
|
|
|
// | 9xyn | Performs a register-register comparison
|
|
//
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | 9XY0 | Skip next instruction if vX != vY |
|
|
impl CPU {
|
|
/// 9xy0: Skip next instruction if X != y
|
|
#[inline]
|
|
fn skip_not_equals(&mut self, x: Reg, y: Reg) {
|
|
if self.v[x] != self.v[y] {
|
|
self.pc = self.pc.wrapping_add(2);
|
|
}
|
|
}
|
|
}
|
|
|
|
// | Aaaa | Load address #a into register I
|
|
impl CPU {
|
|
/// Aadr: Load address #adr into register I
|
|
#[inline]
|
|
fn load_i_immediate(&mut self, a: Adr) {
|
|
self.i = a;
|
|
}
|
|
}
|
|
|
|
// | Baaa | Jump to &adr + v0
|
|
impl CPU {
|
|
/// Badr: Jump to &adr + v0
|
|
///
|
|
/// Quirk:
|
|
/// On the Super-Chip, this does stupid shit
|
|
#[inline]
|
|
fn jump_indexed(&mut self, a: Adr) {
|
|
let reg = if self.flags.quirks.stupid_jumps {
|
|
a as usize >> 8
|
|
} else {
|
|
0
|
|
};
|
|
self.pc = a.wrapping_add(self.v[reg] as Adr);
|
|
}
|
|
}
|
|
|
|
// | Cxbb | Stores a random number + the provided byte into vX
|
|
impl CPU {
|
|
/// Cxbb: Stores a random number & the provided byte into vX
|
|
#[inline]
|
|
fn rand(&mut self, x: Reg, b: u8) {
|
|
self.v[x] = random::<u8>() & b;
|
|
}
|
|
}
|
|
|
|
// | Dxyn | Draws n-byte sprite to the screen at coordinates (vX, vY)
|
|
impl CPU {
|
|
/// Dxyn: Draws n-byte sprite to the screen at coordinates (vX, vY)
|
|
///
|
|
/// # Quirk
|
|
/// On the original chip-8 interpreter, this will wait for a VBI
|
|
fn draw(&mut self, x: Reg, y: Reg, n: Nib, bus: &mut Bus) {
|
|
let (x, y) = (self.v[x] as u16 % 64, self.v[y] as u16 % 32);
|
|
if self.flags.quirks.draw_wait {
|
|
self.flags.vbi_wait = true;
|
|
}
|
|
self.v[0xf] = 0;
|
|
for byte in 0..n as u16 {
|
|
if y + byte > 32 {
|
|
return;
|
|
}
|
|
// Calculate the lower bound address based on the X,Y position on the screen
|
|
let addr = (y + byte) * 8 + (x & 0x3f) / 8 + self.screen;
|
|
// Read a byte of sprite data into a u16, and shift it x % 8 bits
|
|
let sprite: u8 = bus.read(self.i + byte);
|
|
let sprite = (sprite as u16) << 8 - (x & 7) & if x % 64 > 56 { 0xff00 } else { 0xffff };
|
|
// Read a u16 from the bus containing the two bytes which might need to be updated
|
|
let mut screen: u16 = bus.read(addr);
|
|
// Save the bits-toggled-off flag if necessary
|
|
if screen & sprite != 0 {
|
|
self.v[0xF] = 1
|
|
}
|
|
// Update the screen word by XORing the sprite byte
|
|
screen ^= sprite;
|
|
// Save the result to the screen
|
|
bus.write(addr, screen);
|
|
}
|
|
}
|
|
}
|
|
|
|
// | Exbb | Skips instruction on value of keypress
|
|
//
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | eX9e | Skip next instruction if key == #X |
|
|
// | eXa1 | Skip next instruction if key != #X |
|
|
impl CPU {
|
|
/// Ex9E: Skip next instruction if key == #X
|
|
#[inline]
|
|
fn skip_key_equals(&mut self, x: Reg) {
|
|
let x = self.v[x] as usize;
|
|
if self.keys[x] {
|
|
self.pc += 2;
|
|
}
|
|
}
|
|
/// ExaE: Skip next instruction if key != #X
|
|
#[inline]
|
|
fn skip_key_not_equals(&mut self, x: Reg) {
|
|
let x = self.v[x] as usize;
|
|
if !self.keys[x] {
|
|
self.pc += 2;
|
|
}
|
|
}
|
|
}
|
|
|
|
// | Fxbb | Performs IO
|
|
//
|
|
// |opcode| effect |
|
|
// |------|------------------------------------|
|
|
// | fX07 | Set vX to value in delay timer |
|
|
// | fX0a | Wait for input, store in vX m |
|
|
// | fX15 | Set sound timer to the value in vX |
|
|
// | fX18 | set delay timer to the value in vX |
|
|
// | fX1e | Add x to I |
|
|
// | fX29 | Load sprite for character x into I |
|
|
// | fX33 | BCD convert X into I[0..3] |
|
|
// | fX55 | DMA Stor from I to registers 0..X |
|
|
// | fX65 | DMA Load from I to registers 0..X |
|
|
impl CPU {
|
|
/// Fx07: Get the current DT, and put it in vX
|
|
/// ```py
|
|
/// vX = DT
|
|
/// ```
|
|
#[inline]
|
|
fn load_delay_timer(&mut self, x: Reg) {
|
|
self.v[x] = self.delay as u8;
|
|
}
|
|
/// Fx0A: Wait for key, then vX = K
|
|
#[inline]
|
|
fn wait_for_key(&mut self, x: Reg) {
|
|
if let Some(key) = self.flags.lastkey {
|
|
self.v[x] = key as u8;
|
|
self.flags.lastkey = None;
|
|
} else {
|
|
self.pc = self.pc.wrapping_sub(2);
|
|
self.flags.keypause = true;
|
|
}
|
|
}
|
|
/// Fx15: Load vX into DT
|
|
/// ```py
|
|
/// DT = vX
|
|
/// ```
|
|
#[inline]
|
|
fn store_delay_timer(&mut self, x: Reg) {
|
|
self.delay = self.v[x] as f64;
|
|
}
|
|
/// Fx18: Load vX into ST
|
|
/// ```py
|
|
/// ST = vX;
|
|
/// ```
|
|
#[inline]
|
|
fn store_sound_timer(&mut self, x: Reg) {
|
|
self.sound = self.v[x] as f64;
|
|
}
|
|
/// Fx1e: Add vX to I,
|
|
/// ```py
|
|
/// I += vX;
|
|
/// ```
|
|
#[inline]
|
|
fn add_i(&mut self, x: Reg) {
|
|
self.i += self.v[x] as u16;
|
|
}
|
|
/// Fx29: Load sprite for character x into I
|
|
/// ```py
|
|
/// I = sprite(X);
|
|
/// ```
|
|
#[inline]
|
|
fn load_sprite(&mut self, x: Reg) {
|
|
self.i = self.font + (5 * (self.v[x] as Adr % 0x10));
|
|
}
|
|
/// Fx33: BCD convert X into I`[0..3]`
|
|
#[inline]
|
|
fn bcd_convert(&mut self, x: Reg, bus: &mut Bus) {
|
|
let x = self.v[x];
|
|
bus.write(self.i.wrapping_add(2), x % 10);
|
|
bus.write(self.i.wrapping_add(1), x / 10 % 10);
|
|
bus.write(self.i, x / 100 % 10);
|
|
}
|
|
/// Fx55: DMA Stor from I to registers 0..X
|
|
///
|
|
/// # Quirk
|
|
/// The original chip-8 interpreter uses I to directly index memory,
|
|
/// with the side effect of leaving I as I+X+1 after the transfer is done.
|
|
#[inline]
|
|
fn store_dma(&mut self, x: Reg, bus: &mut Bus) {
|
|
let i = self.i as usize;
|
|
for (reg, value) in bus
|
|
.get_mut(i..=i + x)
|
|
.unwrap_or_default()
|
|
.iter_mut()
|
|
.enumerate()
|
|
{
|
|
*value = self.v[reg]
|
|
}
|
|
if self.flags.quirks.dma_inc {
|
|
self.i += x as Adr + 1;
|
|
}
|
|
}
|
|
/// Fx65: DMA Load from I to registers 0..X
|
|
///
|
|
/// # Quirk
|
|
/// The original chip-8 interpreter uses I to directly index memory,
|
|
/// with the side effect of leaving I as I+X+1 after the transfer is done.
|
|
#[inline]
|
|
fn load_dma(&mut self, x: Reg, bus: &mut Bus) {
|
|
let i = self.i as usize;
|
|
for (reg, value) in bus
|
|
.get(i + 0..=i + x)
|
|
.unwrap_or_default()
|
|
.iter()
|
|
.enumerate()
|
|
{
|
|
self.v[reg] = *value;
|
|
}
|
|
if self.flags.quirks.dma_inc {
|
|
self.i += x as Adr + 1;
|
|
}
|
|
}
|
|
}
|