751 lines
24 KiB
Rust
751 lines
24 KiB
Rust
// (c) 2023 John A. Breaux
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// This code is licensed under MIT license (see LICENSE for details)
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//! Contains implementations for each Chip-8 [Insn]
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use super::*;
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use crate::traits::Grab;
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use rand::random;
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impl CPU {
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/// Executes a single [Insn]
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#[rustfmt::skip]
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#[inline(always)]
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pub(super) fn execute(&mut self, screen: &mut Screen, instruction: Insn) {
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match instruction {
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// Core Chip-8 instructions
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Insn::cls => self.clear_screen(screen),
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Insn::ret => self.ret(),
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Insn::jmp { A } => self.jump(A),
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Insn::call { A } => self.call(A),
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Insn::seb { x, B } => self.skip_equals_immediate(x, B),
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Insn::sneb { x, B } => self.skip_not_equals_immediate(x, B),
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Insn::se { y, x } => self.skip_equals(x, y),
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Insn::movb { x, B } => self.load_immediate(x, B),
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Insn::addb { x, B } => self.add_immediate(x, B),
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Insn::mov { y, x } => self.load(x, y),
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Insn::or { y, x } => self.or(x, y),
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Insn::and { y, x } => self.and(x, y),
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Insn::xor { y, x } => self.xor(x, y),
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Insn::add { y, x } => self.add(x, y),
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Insn::sub { y, x } => self.sub(x, y),
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Insn::shr { y, x } => self.shift_right(x, y),
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Insn::bsub { y, x } => self.backwards_sub(x, y),
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Insn::shl { y, x } => self.shift_left(x, y),
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Insn::sne { y, x } => self.skip_not_equals(x, y),
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Insn::movI { A } => self.load_i_immediate(A),
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Insn::jmpr { A } => self.jump_indexed(A),
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Insn::rand { x, B } => self.rand(x, B),
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Insn::draw { y, x, n } => self.draw(x, y, n, screen),
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Insn::sek { x } => self.skip_key_equals(x),
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Insn::snek { x } => self.skip_key_not_equals(x),
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Insn::getdt { x } => self.load_delay_timer(x),
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Insn::waitk { x } => self.wait_for_key(x),
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Insn::setdt { x } => self.store_delay_timer(x),
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Insn::movst { x } => self.store_sound_timer(x),
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Insn::addI { x } => self.add_i(x),
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Insn::font { x } => self.load_sprite(x),
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Insn::bcd { x } => self.bcd_convert(x),
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Insn::dmao { x } => self.store_dma(x),
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Insn::dmai { x } => self.load_dma(x),
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// Super-Chip extensions
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Insn::scd { n } => self.scroll_down(n, screen),
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Insn::scr => self.scroll_right(screen),
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Insn::scl => self.scroll_left(screen),
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Insn::halt => self.flags.pause(),
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Insn::lores => self.init_lores(screen),
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Insn::hires => self.init_hires(screen),
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Insn::hfont { x } => self.load_big_sprite(x),
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Insn::flgo { x } => self.store_flags(x),
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Insn::flgi { x } => self.load_flags(x),
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// XO-Chip extensions
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_ => unimplemented!(),
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}
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}
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}
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/// |`0aaa`| Issues a "System call" (ML routine)
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///
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/// |opcode| effect |
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/// |------|------------------------------------|
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/// |`00e0`| Clear screen memory to all 0 |
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/// |`00ee`| Return from subroutine |
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impl CPU {
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/// |`00e0`| Clears the screen memory to 0
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/// Corresponds to [Insn::cls]
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#[inline(always)]
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pub(super) fn clear_screen(&mut self, screen: &mut Screen) {
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screen.clear()
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}
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/// |`00ee`| Returns from subroutine
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/// Corresponds to [Insn::ret]
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#[inline(always)]
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pub(super) fn ret(&mut self) {
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self.pc = self.stack.pop().unwrap_or(0x200);
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}
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}
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/// Super Chip screen-control routines
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///
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/// |opcode| effect |
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/// |------|------------------------------------|
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/// |`00cN`| Scroll the screen down N lines |
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/// |`00fb`| Scroll the screen right |
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/// |`00fc`| Scroll the screen left |
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/// |`00fe`| Initialize lores mode |
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/// |`00ff`| Initialize hires mode |
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impl CPU {
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/// # |`00cN`|
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/// Scroll the screen down N lines
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///
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/// Corresponds to [Insn::scd]
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#[inline(always)]
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pub(super) fn scroll_down(&mut self, n: Nib, screen: &mut Screen) {
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match self.flags.draw_mode {
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true => {
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// Get a line from the bus
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for i in (0..16 * (64 - n as usize)).step_by(16).rev() {
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let line: u128 = screen.read(i);
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screen.write(i - (n as usize * 16), 0u128);
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screen.write(i, line);
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}
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}
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false => {
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// Get a line from the bus
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for i in (0..8 * (32 - n as usize)).step_by(8).rev() {
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let line: u64 = screen.read(i);
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screen.write(i, 0u64);
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screen.write(i + (n as usize * 8), line);
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}
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}
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}
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}
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/// # |`00fb`|
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/// Scroll the screen right
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///
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/// Corresponds to [Insn::scr]
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#[inline(always)]
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pub(super) fn scroll_right(&mut self, screen: &mut impl AutoCast<u128>) {
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// Get a line from the bus
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for i in (0..16 * 64_usize).step_by(16) {
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//let line: u128 = bus.read(self.screen + i) >> 4;
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screen.write(i, screen.read(i) >> 4);
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}
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}
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/// # |`00fc`|
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/// Scroll the screen left
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///
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/// Corresponds to [Insn::scl]
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#[inline(always)]
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pub(super) fn scroll_left(&mut self, screen: &mut impl AutoCast<u128>) {
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// Get a line from the bus
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for i in (0..16 * 64_usize).step_by(16) {
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let line: u128 = u128::wrapping_shl(screen.read(i), 4);
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screen.write(i, line);
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}
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}
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/// # |`00fe`|
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/// Initialize lores mode
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///
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/// Corresponds to [Insn::lores]
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pub(super) fn init_lores(&mut self, screen: &mut Screen) {
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self.flags.draw_mode = false;
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screen.with_size(256);
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self.clear_screen(screen);
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}
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/// # |`00ff`|
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/// Initialize hires mode
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///
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/// Corresponds to [Insn::hires]
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pub(super) fn init_hires(&mut self, screen: &mut Screen) {
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self.flags.draw_mode = true;
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screen.with_size(1024);
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self.clear_screen(screen);
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}
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}
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/// |`1aaa`| Sets pc to an absolute address
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impl CPU {
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/// |`1aaa`| Sets the program counter to an absolute address
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///
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/// Corresponds to [Insn::jmp]
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#[inline(always)]
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pub(super) fn jump(&mut self, a: Adr) {
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// jump to self == halt
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if a.wrapping_add(2) == self.pc {
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self.flags.pause = true;
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}
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self.pc = a;
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}
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}
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/// |`2aaa`| Pushes pc onto the stack, then jumps to a
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impl CPU {
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/// |`2aaa`| Pushes pc onto the stack, then jumps to a
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///
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/// Corresponds to [Insn::call]
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#[inline(always)]
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pub(super) fn call(&mut self, a: Adr) {
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self.stack.push(self.pc);
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self.pc = a;
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}
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}
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/// |`3xbb`| Skips next instruction if register X == b
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impl CPU {
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/// |`3xbb`| Skips the next instruction if register X == b
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///
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/// Corresponds to [Insn::seb]
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#[inline(always)]
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pub(super) fn skip_equals_immediate(&mut self, x: Reg, b: u8) {
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if self.v[x] == b {
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self.pc = self.pc.wrapping_add(2);
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}
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}
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}
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/// |`4xbb`| Skips next instruction if register X != b
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impl CPU {
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/// |`4xbb`| Skips the next instruction if register X != b
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///
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/// Corresponds to [Insn::sneb]
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#[inline(always)]
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pub(super) fn skip_not_equals_immediate(&mut self, x: Reg, b: u8) {
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if self.v[x] != b {
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self.pc = self.pc.wrapping_add(2);
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}
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}
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}
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/// |`5xyn`| Performs a register-register comparison
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///
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/// |opcode| effect |
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/// |------|------------------------------------|
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/// |`5XY0`| Skip next instruction if vX == vY |
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impl CPU {
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/// |`5xy0`| Skips the next instruction if register X != register Y
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///
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/// Corresponds to [Insn::sne]
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#[inline(always)]
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pub(super) fn skip_equals(&mut self, x: Reg, y: Reg) {
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if self.v[x] == self.v[y] {
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self.pc = self.pc.wrapping_add(2);
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}
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}
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}
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/// |`6xbb`| Loads immediate byte b into register vX
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impl CPU {
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/// |`6xbb`| Loads immediate byte b into register vX
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///
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/// Corresponds to [Insn::movb]
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#[inline(always)]
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pub(super) fn load_immediate(&mut self, x: Reg, b: u8) {
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self.v[x] = b;
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}
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}
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/// |`7xbb`| Adds immediate byte b to register vX
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impl CPU {
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/// |`7xbb`| Adds immediate byte b to register vX
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///
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/// Corresponds to [Insn::addb]
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#[inline(always)]
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pub(super) fn add_immediate(&mut self, x: Reg, b: u8) {
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self.v[x] = self.v[x].wrapping_add(b);
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}
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}
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/// |`8xyn`| Performs ALU operation
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///
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/// |opcode| effect |
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/// |------|------------------------------------|
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/// |`8xy0`| Y = X |
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/// |`8xy1`| X = X | Y |
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/// |`8xy2`| X = X & Y |
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/// |`8xy3`| X = X ^ Y |
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/// |`8xy4`| X = X + Y; Set vF=carry |
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/// |`8xy5`| X = X - Y; Set vF=carry |
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/// |`8xy6`| X = X >> 1 |
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/// |`8xy7`| X = Y - X; Set vF=carry |
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/// |`8xyE`| X = X << 1 |
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impl CPU {
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/// |`8xy0`| Loads the value of y into x
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///
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/// Corresponds to [Insn::mov]
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#[inline(always)]
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pub(super) fn load(&mut self, x: Reg, y: Reg) {
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self.v[x] = self.v[y];
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}
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/// |`8xy1`| Performs bitwise or of vX and vY, and stores the result in vX
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///
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/// Corresponds to [Insn::or]
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///
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/// # Quirk
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline(always)]
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pub(super) fn or(&mut self, x: Reg, y: Reg) {
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self.v[x] |= self.v[y];
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if !self.flags.quirks.bin_ops {
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self.v[0xf] = 0;
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}
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}
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/// |`8xy2`| Performs bitwise and of vX and vY, and stores the result in vX
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///
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/// Corresponds to [Insn::and]
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///
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/// # Quirk
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline(always)]
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pub(super) fn and(&mut self, x: Reg, y: Reg) {
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self.v[x] &= self.v[y];
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if !self.flags.quirks.bin_ops {
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self.v[0xf] = 0;
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}
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}
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/// |`8xy3`| Performs bitwise xor of vX and vY, and stores the result in vX
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///
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/// Corresponds to [Insn::xor]
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///
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/// # Quirk
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline(always)]
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pub(super) fn xor(&mut self, x: Reg, y: Reg) {
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self.v[x] ^= self.v[y];
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if !self.flags.quirks.bin_ops {
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self.v[0xf] = 0;
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}
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}
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/// |`8xy4`| Performs addition of vX and vY, and stores the result in vX
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///
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/// Corresponds to [Insn::add]
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#[inline(always)]
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pub(super) fn add(&mut self, x: Reg, y: Reg) {
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let carry;
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(self.v[x], carry) = self.v[x].overflowing_add(self.v[y]);
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self.v[0xf] = carry.into();
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}
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/// |`8xy5`| Performs subtraction of vX and vY, and stores the result in vX
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///
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/// Corresponds to [Insn::sub]
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#[inline(always)]
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pub(super) fn sub(&mut self, x: Reg, y: Reg) {
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let carry;
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(self.v[x], carry) = self.v[x].overflowing_sub(self.v[y]);
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self.v[0xf] = (!carry).into();
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}
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/// |`8xy6`| Performs bitwise right shift of vX
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///
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/// Corresponds to [Insn::shr]
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///
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/// # Quirk
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/// On the original chip-8 interpreter, this shifts vY and stores the result in vX
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#[inline(always)]
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pub(super) fn shift_right(&mut self, x: Reg, y: Reg) {
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let src: Reg = if self.flags.quirks.shift { x } else { y };
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let shift_out = self.v[src] & 1;
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self.v[x] = self.v[src] >> 1;
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self.v[0xf] = shift_out;
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}
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/// |`8xy7`| Performs subtraction of vY and vX, and stores the result in vX
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///
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/// Corresponds to [Insn::bsub]
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#[inline(always)]
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pub(super) fn backwards_sub(&mut self, x: Reg, y: Reg) {
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let carry;
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(self.v[x], carry) = self.v[y].overflowing_sub(self.v[x]);
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self.v[0xf] = (!carry).into();
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}
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/// 8X_E: Performs bitwise left shift of vX
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///
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/// Corresponds to [Insn::shl]
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///
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/// # Quirk
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/// On the original chip-8 interpreter, this would perform the operation on vY
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/// and store the result in vX. This behavior was left out, for now.
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#[inline(always)]
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pub(super) fn shift_left(&mut self, x: Reg, y: Reg) {
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let src: Reg = if self.flags.quirks.shift { x } else { y };
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let shift_out: u8 = self.v[src] >> 7;
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self.v[x] = self.v[src] << 1;
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self.v[0xf] = shift_out;
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}
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}
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/// |`9xyn`| Performs a register-register comparison
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///
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/// |opcode| effect |
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/// |------|------------------------------------|
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/// |`9XY0`| Skip next instruction if vX != vY |
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impl CPU {
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/// |`9xy0`| Skip next instruction if X != y
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///
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/// Corresponds to [Insn::sne]
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#[inline(always)]
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pub(super) fn skip_not_equals(&mut self, x: Reg, y: Reg) {
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if self.v[x] != self.v[y] {
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self.pc = self.pc.wrapping_add(2);
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}
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}
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}
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/// |`Aaaa`| Load address #a into register I
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impl CPU {
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/// |`Aadr`| Load address #adr into register I
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///
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/// Corresponds to [Insn::movI]
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#[inline(always)]
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pub(super) fn load_i_immediate(&mut self, a: Adr) {
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self.i = a;
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}
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}
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/// |`Baaa`| Jump to &adr + v0
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impl CPU {
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/// |`Badr`| Jump to &adr + v0
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///
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/// Corresponds to [Insn::jmpr]
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///
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/// Quirk:
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/// On the Super-Chip, this does stupid shit
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#[inline(always)]
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pub(super) fn jump_indexed(&mut self, a: Adr) {
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let reg = if self.flags.quirks.stupid_jumps {
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a as usize >> 8
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} else {
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0
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};
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self.pc = a.wrapping_add(self.v[reg] as Adr);
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}
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}
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/// |`Cxbb`| Stores a random number & the provided byte into vX
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impl CPU {
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/// |`Cxbb`| Stores a random number & the provided byte into vX
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///
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/// Corresponds to [Insn::rand]
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#[inline(always)]
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pub(super) fn rand(&mut self, x: Reg, b: u8) {
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self.v[x] = random::<u8>() & b;
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}
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}
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/// |`Dxyn`| Draws n-byte sprite to the screen at coordinates (vX, vY)
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impl CPU {
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/// |`Dxyn`| Draws n-byte sprite to the screen at coordinates (vX, vY)
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///
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/// Corresponds to [Insn::draw]
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///
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/// # Quirk
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/// On the original chip-8 interpreter, this will wait for a VBI
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#[inline(always)]
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pub(super) fn draw(&mut self, x: Reg, y: Reg, n: Nib, screen: &mut Screen) {
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if !self.flags.quirks.draw_wait {
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self.flags.draw_wait = true;
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}
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// self.draw_hires handles both hi-res mode and drawing 16x16 sprites
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if self.flags.draw_mode || n == 0 {
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self.draw_hires(x, y, n, screen);
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} else {
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self.draw_lores(x, y, n, screen);
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}
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}
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/// |`Dxyn`| Chip-8: Draws n-byte sprite to the screen at coordinates (vX, vY)
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#[inline(always)]
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pub(super) fn draw_lores(&mut self, x: Reg, y: Reg, n: Nib, scr: &mut Screen) {
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self.draw_sprite(self.v[x] as u16 % 64, self.v[y] as u16 % 32, n, 64, 32, scr);
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|
}
|
|
|
|
#[inline(always)]
|
|
pub(super) fn draw_sprite(
|
|
&mut self,
|
|
x: u16,
|
|
y: u16,
|
|
n: Nib,
|
|
w: u16,
|
|
h: u16,
|
|
screen: &mut Screen,
|
|
) {
|
|
let w_bytes = w / 8;
|
|
self.v[0xf] = 0;
|
|
if let Some(sprite) = self.mem.grab(self.i as usize..(self.i + n as u16) as usize) {
|
|
for (line, &sprite) in sprite.iter().enumerate() {
|
|
let line = line as u16;
|
|
let sprite = ((sprite as u16) << (8 - (x % 8))).to_be_bytes();
|
|
for (addr, &byte) in sprite.iter().enumerate().filter_map(|(idx, byte)| {
|
|
let x = (x / 8) + idx as u16;
|
|
Some((
|
|
if self.flags.quirks.screen_wrap {
|
|
((y + line) % h * w_bytes + (x % w_bytes)) % (w_bytes * h)
|
|
} else if x < w_bytes {
|
|
(y + line) * w_bytes + x
|
|
} else {
|
|
return None;
|
|
},
|
|
byte,
|
|
))
|
|
}) {
|
|
let display: u8 = screen.read(addr);
|
|
screen.write(addr, byte ^ display);
|
|
if byte & display != 0 {
|
|
self.v[0xf] = 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/// |`Dxyn`| Super-Chip extension high-resolution graphics mode
|
|
impl CPU {
|
|
/// |`Dxyn`| Super-Chip extension high-resolution graphics mode
|
|
#[inline(always)]
|
|
pub(super) fn draw_hires(&mut self, x: Reg, y: Reg, n: Nib, screen: &mut Screen) {
|
|
if !self.flags.quirks.draw_wait {
|
|
self.flags.draw_wait = true;
|
|
}
|
|
let (w, h) = match self.flags.draw_mode {
|
|
true => (128, 64),
|
|
false => (64, 32),
|
|
};
|
|
let (x, y) = (self.v[x] as u16 % w, self.v[y] as u16 % h);
|
|
match n {
|
|
0 => self.draw_schip_sprite(x, y, w, screen),
|
|
_ => self.draw_sprite(x, y, n, w, h, screen),
|
|
}
|
|
}
|
|
/// Draws a 16x16 Super Chip sprite
|
|
#[inline(always)]
|
|
pub(super) fn draw_schip_sprite(&mut self, x: u16, y: u16, w: u16, screen: &mut Screen) {
|
|
self.v[0xf] = 0;
|
|
let w_bytes = w / 8;
|
|
if let Some(sprite) = self.mem.grab(self.i as usize..(self.i + 32) as usize) {
|
|
let sprite = sprite.to_owned();
|
|
for (line, sprite) in sprite.chunks_exact(2).enumerate() {
|
|
let sprite = u16::from_be_bytes(
|
|
sprite
|
|
.try_into()
|
|
.expect("Chunks should only return 2 bytes"),
|
|
);
|
|
let addr = (y + line as u16) * w_bytes + x / 8;
|
|
let sprite = (sprite as u32) << (16 - (x % 8));
|
|
let display: u32 = screen.read(addr);
|
|
screen.write(addr, display ^ sprite);
|
|
if display & sprite != 0 {
|
|
self.v[0xf] += 1;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/// |`Exbb`| Skips instruction on value of keypress
|
|
///
|
|
/// |opcode| effect |
|
|
/// |------|------------------------------------|
|
|
/// |`eX9e`| Skip next instruction if key == vX |
|
|
/// |`eXa1`| Skip next instruction if key != vX |
|
|
impl CPU {
|
|
/// |`Ex9E`| Skip next instruction if key == vX
|
|
///
|
|
/// Corresponds to [Insn::sek]
|
|
#[inline(always)]
|
|
pub(super) fn skip_key_equals(&mut self, x: Reg) {
|
|
if self.keys[self.v[x] as usize & 0xf] {
|
|
self.pc += 2;
|
|
}
|
|
}
|
|
/// |`ExaE`| Skip next instruction if key != vX
|
|
///
|
|
/// Corresponds to [Insn::snek]
|
|
#[inline(always)]
|
|
pub(super) fn skip_key_not_equals(&mut self, x: Reg) {
|
|
if !self.keys[self.v[x] as usize & 0xf] {
|
|
self.pc += 2;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// |`Fxbb`| Performs IO
|
|
///
|
|
/// |opcode| effect |
|
|
/// |------|------------------------------------|
|
|
/// |`fX07`| Set vX to value in delay timer |
|
|
/// |`fX0a`| Wait for input, store key in vX |
|
|
/// |`fX15`| Set sound timer to the value in vX |
|
|
/// |`fX18`| set delay timer to the value in vX |
|
|
/// |`fX1e`| Add vX to I |
|
|
/// |`fX29`| Load sprite for character x into I |
|
|
/// |`fX33`| BCD convert X into I[0..3] |
|
|
/// |`fX55`| DMA Stor from I to registers 0..=X |
|
|
/// |`fX65`| DMA Load from I to registers 0..=X |
|
|
impl CPU {
|
|
/// |`Fx07`| Get the current DT, and put it in vX
|
|
///
|
|
/// Corresponds to [Insn::getdt]
|
|
///
|
|
/// ```py
|
|
/// vX = DT
|
|
/// ```
|
|
#[inline(always)]
|
|
pub(super) fn load_delay_timer(&mut self, x: Reg) {
|
|
self.v[x] = self.delay;
|
|
}
|
|
/// |`Fx0A`| Wait for key, then vX = K
|
|
#[inline(always)]
|
|
pub(super) fn wait_for_key(&mut self, x: Reg) {
|
|
if let Some(key) = self.lastkey {
|
|
self.v[x] = key as u8;
|
|
self.lastkey = None;
|
|
} else {
|
|
self.pc = self.pc.wrapping_sub(2);
|
|
self.flags.keypause = true;
|
|
}
|
|
}
|
|
/// |`Fx15`| Load vX into DT
|
|
///
|
|
/// Corresponds to [Insn::setdt]
|
|
/// ```py
|
|
/// DT = vX
|
|
/// ```
|
|
#[inline(always)]
|
|
pub(super) fn store_delay_timer(&mut self, x: Reg) {
|
|
self.delay = self.v[x];
|
|
}
|
|
/// |`Fx18`| Load vX into ST
|
|
///
|
|
/// Corresponds to [Insn::movst]
|
|
/// ```py
|
|
/// ST = vX;
|
|
/// ```
|
|
#[inline(always)]
|
|
pub(super) fn store_sound_timer(&mut self, x: Reg) {
|
|
self.sound = self.v[x];
|
|
}
|
|
/// |`Fx1e`| Add vX to I,
|
|
///
|
|
/// Corresponds to [Insn::addI]
|
|
/// ```py
|
|
/// I += vX;
|
|
/// ```
|
|
#[inline(always)]
|
|
pub(super) fn add_i(&mut self, x: Reg) {
|
|
self.i += self.v[x] as u16;
|
|
}
|
|
/// |`Fx29`| Load sprite for character x into I
|
|
///
|
|
/// Corresponds to [Insn::font]
|
|
/// ```py
|
|
/// I = sprite(X);
|
|
/// ```
|
|
#[inline(always)]
|
|
pub(super) fn load_sprite(&mut self, x: Reg) {
|
|
self.i = self.font + (5 * (self.v[x] as Adr % 0x10));
|
|
}
|
|
/// |`Fx33`| BCD convert X into I`[0..3]`
|
|
///
|
|
/// Corresponds to [Insn::bcd]
|
|
#[inline(always)]
|
|
pub(super) fn bcd_convert(&mut self, x: Reg) {
|
|
let x = self.v[x];
|
|
self.mem.write(self.i.wrapping_add(2), x % 10);
|
|
self.mem.write(self.i.wrapping_add(1), x / 10 % 10);
|
|
self.mem.write(self.i, x / 100 % 10);
|
|
}
|
|
/// |`Fx55`| DMA Stor from I to registers 0..=X
|
|
///
|
|
/// Corresponds to [Insn::dmao]
|
|
///
|
|
/// # Quirk
|
|
/// The original chip-8 interpreter uses I to directly index memory,
|
|
/// with the side effect of leaving I as I+X+1 after the transfer is done.
|
|
#[inline(always)]
|
|
pub(super) fn store_dma(&mut self, x: Reg) {
|
|
let i = self.i as usize;
|
|
for (reg, value) in self
|
|
.mem
|
|
.grab_mut(i..=i + x)
|
|
.unwrap_or_default()
|
|
.iter_mut()
|
|
.enumerate()
|
|
{
|
|
*value = self.v[reg]
|
|
}
|
|
if !self.flags.quirks.dma_inc {
|
|
self.i += x as Adr + 1;
|
|
}
|
|
}
|
|
/// |`Fx65`| DMA Load from I to registers 0..=X
|
|
///
|
|
/// Corresponds to [Insn::dmai]
|
|
///
|
|
/// # Quirk
|
|
/// The original chip-8 interpreter uses I to directly index memory,
|
|
/// with the side effect of leaving I as I+X+1 after the transfer is done.
|
|
#[inline(always)]
|
|
pub(super) fn load_dma(&mut self, x: Reg) {
|
|
let i = self.i as usize;
|
|
for (reg, value) in self
|
|
.mem
|
|
.grab(i..=i + x)
|
|
.unwrap_or_default()
|
|
.iter()
|
|
.enumerate()
|
|
{
|
|
self.v[reg] = *value;
|
|
}
|
|
if !self.flags.quirks.dma_inc {
|
|
self.i += x as Adr + 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/// |`Fxbb`| Super Chip: Performs IO
|
|
///
|
|
/// |opcode| effect |
|
|
/// |------|------------------------------------|
|
|
/// |`Fx30`| 16x16 equivalent of load_sprite |
|
|
/// |`Fx75`| Save to "flag registers" |
|
|
/// |`Fx85`| Load from "flag registers" |
|
|
impl CPU {
|
|
/// |`Fx30`| (Super-Chip) 16x16 equivalent of [CPU::load_sprite]
|
|
///
|
|
/// Corresponds to [Insn::hfont]
|
|
///
|
|
/// TODO: Actually make and import the 16x font
|
|
#[inline(always)]
|
|
pub(super) fn load_big_sprite(&mut self, x: Reg) {
|
|
self.i = self.font + (5 * 8) + (16 * (self.v[x] as Adr % 0x10));
|
|
}
|
|
|
|
/// |`Fx75`| (Super-Chip) Save to "flag registers"
|
|
/// I just chuck it in 0x0..0xf. Screw it.
|
|
///
|
|
/// Corresponds to [Insn::flgo]
|
|
#[inline(always)]
|
|
pub(super) fn store_flags(&mut self, x: Reg) {
|
|
// TODO: Save these, maybe
|
|
for (reg, value) in self
|
|
.mem
|
|
.grab_mut(0..=x)
|
|
.unwrap_or_default()
|
|
.iter_mut()
|
|
.enumerate()
|
|
{
|
|
*value = self.v[reg]
|
|
}
|
|
}
|
|
|
|
/// |`Fx85`| (Super-Chip) Load from "flag registers"
|
|
/// I just chuck it in 0x0..0xf. Screw it.
|
|
///
|
|
/// Corresponds to [Insn::flgi]
|
|
#[inline(always)]
|
|
pub(super) fn load_flags(&mut self, x: Reg) {
|
|
for (reg, value) in self.mem.grab(0..=x).unwrap_or_default().iter().enumerate() {
|
|
self.v[reg] = *value;
|
|
}
|
|
}
|
|
}
|