John Breaux
ef3d765651
- Do some basic benchmarking with std::time
- Try writing bus writer based on iterator
- Fail, because that requires mutable iterator
- Begin rewriting bus based on simpler design instead.
- Simpler design uses a unified memory model,
which grows based on the maximum addresses expected in it
- Still uses the "infallible" Read/Write traits from previous
implementation. :( Alas, it's much faster during operation,
even if it takes longer to instantiate.
- Reassessed the syntax for bus macro
- Made CPU tick generic over bus::Read and bus::Write traits
55 lines
1.4 KiB
Rust
55 lines
1.4 KiB
Rust
//! Connects a BusConnectible to the Bus
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use super::BusConnectible;
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use std::{
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fmt::{Display, Formatter, Result},
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ops::Range,
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};
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/// BusDevice performs address translation for BusConnectibles.
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/// It is an implementation detail of Bus.connect()
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#[derive(Debug)]
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pub struct BusDevice {
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pub name: String,
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pub range: Range<u16>,
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device: Box<dyn BusConnectible>,
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}
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impl BusDevice {
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pub fn new(name: &str, range: Range<u16>, device: Box<dyn BusConnectible>) -> Self {
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BusDevice {
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name: name.to_string(),
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range,
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device,
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}
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}
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fn translate_address(&self, addr: u16) -> Option<u16> {
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let addr = addr.wrapping_sub(self.range.start);
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if addr < self.range.end {
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Some(addr)
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} else {
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None
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}
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}
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}
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impl BusConnectible for BusDevice {
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fn read_at(&self, addr: u16) -> Option<u8> {
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self.device.read_at(self.translate_address(addr)?)
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}
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fn write_to(&mut self, addr: u16, data: u8) {
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if let Some(addr) = self.translate_address(addr) {
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self.device.write_to(addr, data);
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}
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}
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fn get_mut(&mut self, addr: u16) -> Option<&mut u8> {
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return self.device.get_mut(addr);
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}
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}
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impl Display for BusDevice {
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fn fmt(&self, f: &mut Formatter<'_>) -> Result {
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writeln!(f, "{} [{:04x?}]:\n{}", self.name, self.range, self.device)
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}
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}
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