j/Chirp
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cc3bc3a7fe
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3 Commits

Author SHA1 Message Date
John Breaux
cc3bc3a7fe Major Refactor: Make invalid states unrepresentable™️ 
- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
  - Now >10x faster
  - Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
  - (use option -S to set the number of instructions per epoch)
 2023-03-30 08:27:06 -05:00
John Breaux
c194a3c53a Error: Remove FunkyMathError and Stringly Typed context 2023-03-29 23:42:41 -05:00
John Breaux
ce0dc954d0 tests: Improve cpu.rs line coverage to >99% 2023-03-28 12:31:56 -05:00