Major Refactor: Make invalid states unrepresentable™️

- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
  - Now >10x faster
  - Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
  - (use option -S to set the number of instructions per epoch)

tests/integration.rs

@@ -236,7 +236,7 @@ mod ui {
         let mut ch8 = new_chip8();
         let ch8 = &mut ch8;
         ui.frame(ch8).unwrap();
-        ui.keys(ch8);
+        ui.keys(ch8).unwrap();
         Ok(())
     }
     #[test]