Major Refactor: Make invalid states unrepresentable™️

- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
  - Now >10x faster
  - Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
  - (use option -S to set the number of instructions per epoch)

tests/chip8_test_suite.rs

@@ -33,7 +33,7 @@ fn run_screentest(test: SuiteTest, mut cpu: CPU, mut bus: Bus) {
     bus = bus.load_region(Program, test.program);
     // The test suite always initiates a keypause on test completion
     while !cpu.flags.keypause {
-        cpu.multistep(&mut bus, 8);
+        cpu.multistep(&mut bus, 8).unwrap();
     }
     // Compare the screen to the reference screen buffer
     bus.print_screen().unwrap();