Major Refactor: Make invalid states unrepresentable™️

- Rewrote the instruction decoder as an enum
- Used imperative_rs to auto-generate the bit twiddling logic
- Implemented Display on that enum, for disassembly
- Rewrote CPU::tick
  - Now >10x faster
  - Disassembly mode is still 5x slower though
- Implemented time-based benchmarking
  - (use option -S to set the number of instructions per epoch)

justfile

@@ -4,7 +4,7 @@ test:
     cargo test --doc && cargo nextest run
 
 chirp:
-    cargo run --bin chirp -- tests/chip8-test-suite/bin/chip8-test-suite.ch8
+    cargo run --bin chirp-minifb -- tests/chip8-test-suite/bin/chip8-test-suite.ch8
 
 cover:
     cargo llvm-cov --open --doctests