From f60a4b3cc2c01af30d0f77f7f733fcf8a88c0f8e Mon Sep 17 00:00:00 2001 From: John Breaux Date: Thu, 30 Mar 2023 02:12:03 -0500 Subject: [PATCH 1/6] Refactor disassembler to use imperative-rs It's like MAGIC. Easily cut out 200 LOC --- Cargo.lock | 22 +++ Cargo.toml | 1 + src/bin/chirp-disasm.rs | 18 +- src/bin/chirp-minifb.rs | 2 +- src/cpu.rs | 21 +- src/cpu/disassembler.rs | 184 ++++++++++++++++++ .../{disassemble.rs => old_disassembler.rs} | 26 ++- src/lib.rs | 2 +- 8 files changed, 249 insertions(+), 27 deletions(-) create mode 100644 src/cpu/disassembler.rs rename src/cpu/{disassemble.rs => old_disassembler.rs} (96%) diff --git a/Cargo.lock b/Cargo.lock index bd52bfe..958386e 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -182,6 +182,7 @@ version = "0.1.0" dependencies = [ "gumdrop", "iced", + "imperative-rs", "minifb", "owo-colors", "rand", @@ -1086,6 +1087,27 @@ version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "b9e0384b61958566e926dc50660321d12159025e767c18e043daf26b70104c39" +[[package]] +name = "imperative-rs" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "fed4f0a3a8fe169e919b74f6ba77c473d356ef05d0d65da06467b8836e508aa3" +dependencies = [ + "imperative-rs-derive", +] + +[[package]] +name = "imperative-rs-derive" +version = "0.3.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "02b842fd8a24b2b715ac0baffae4aa72aa59ecb8e90d3de175180dbb5b1caaab" +dependencies = [ + "lazy_static", + "proc-macro2", + "quote", + "syn 1.0.109", +] + [[package]] name = "indexmap" version = "1.9.3" diff --git a/Cargo.toml b/Cargo.toml index 2be055b..75e6eb6 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -28,6 +28,7 @@ overflow-checks = false [dependencies] gumdrop = "^0.8.1" iced = {version = "0.8.0", optional = true} +imperative-rs = "0.3.1" minifb = { version = "^0.24.0", features = ["wayland"] } owo-colors = "^3" rand = "^0.8.5" diff --git a/src/bin/chirp-disasm.rs b/src/bin/chirp-disasm.rs index c65f633..0c8a893 100644 --- a/src/bin/chirp-disasm.rs +++ b/src/bin/chirp-disasm.rs @@ -1,7 +1,7 @@ -use chirp::{error::Result, prelude::*}; +use chirp::{cpu::Disassembler, error::Result, prelude::*}; use gumdrop::*; -use std::{fs::read, path::PathBuf}; use owo_colors::OwoColorize; +use std::{fs::read, path::PathBuf}; #[derive(Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Options, Hash)] struct Arguments { @@ -22,18 +22,20 @@ fn parse_hex(value: &str) -> std::result::Result { fn main() -> Result<()> { let options = Arguments::parse_args_default_or_exit(); let contents = &read(&options.file)?; - let disassembler = Disassemble::default(); + let disassembler = Dis::default(); for (addr, insn) in contents[options.offset..].chunks_exact(2).enumerate() { let insn = u16::from_be_bytes( insn.try_into() .expect("Iterated over 2-byte chunks, got <2 bytes"), ); println!( - "{:03x}: {} {:04x}", - 2 * addr + 0x200 + options.offset, - disassembler.instruction(insn), - insn.bright_black(), - + "{}", + format_args!( + "{:03x}: {} {:04x}", + 2 * addr + 0x200 + options.offset, + disassembler.once(insn), + insn.bright_black(), + ) ); } Ok(()) diff --git a/src/bin/chirp-minifb.rs b/src/bin/chirp-minifb.rs index 256dce0..3ba905e 100644 --- a/src/bin/chirp-minifb.rs +++ b/src/bin/chirp-minifb.rs @@ -104,7 +104,7 @@ impl State { 0x50, 0x200, 0xefe, - Disassemble::default(), + Dis::default(), options.breakpoints, ControlFlags { quirks: chirp::cpu::Quirks { diff --git a/src/cpu.rs b/src/cpu.rs index 85a6b75..3f3744d 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -6,9 +6,16 @@ #[cfg(test)] mod tests; -pub mod disassemble; +/// Disassembles Chip-8 instructions +pub trait Disassembler { + /// Disassemble a single instruction + fn once(&self, insn: u16) -> String; +} -use self::disassemble::Disassemble; +pub mod disassembler; +pub mod old_disassembler; + +use self::disassembler::Dis; use crate::bus::{Bus, Read, Region, Write}; use owo_colors::OwoColorize; use rand::random; @@ -138,7 +145,7 @@ pub struct CPU { timer: Instant, cycle: usize, breakpoints: Vec, - disassembler: Disassemble, + disassembler: Dis, } // public interface @@ -164,7 +171,7 @@ impl CPU { font: Adr, pc: Adr, sp: Adr, - disassembler: Disassemble, + disassembler: Dis, breakpoints: Vec, flags: ControlFlags, ) -> Self { @@ -549,7 +556,7 @@ impl CPU { self.pc = self.pc.wrapping_add(2); // decode opcode - use disassemble::{a, b, i, n, x, y}; + use old_disassembler::{a, b, i, n, x, y}; let (i, x, y, n, b, a) = ( i(opcode), x(opcode), @@ -674,7 +681,7 @@ impl CPU { "{:3} {:03x}: {:<36}{:?}", self.cycle.bright_black(), pc, - self.disassembler.instruction(opcode), + self.disassembler.once(opcode), elapsed.dimmed() ); } @@ -765,7 +772,7 @@ impl Default for CPU { }, timer: Instant::now(), breakpoints: vec![], - disassembler: Disassemble::default(), + disassembler: Dis::default(), } } } diff --git a/src/cpu/disassembler.rs b/src/cpu/disassembler.rs new file mode 100644 index 0000000..b1825f1 --- /dev/null +++ b/src/cpu/disassembler.rs @@ -0,0 +1,184 @@ +//! A disassembler for Chip-8 opcodes + +use super::Disassembler; +use imperative_rs::InstructionSet; +use owo_colors::{OwoColorize, Style}; +use std::fmt::Display; + +#[allow(non_camel_case_types, non_snake_case, missing_docs)] +#[derive(Clone, Copy, InstructionSet, PartialEq, Eq, PartialOrd, Ord, Hash)] +/// Implements a Disassembler using imperative_rs +pub enum Insn { + /// | 00e0 | Clear screen memory to 0s + #[opcode = "0x00e0"] + cls, + /// | 00ee | Return from subroutine + #[opcode = "0x00ee"] + ret, + /// | 1aaa | Jumps to an absolute address + #[opcode = "0x1AAA"] + jmp { A: u16 }, + /// | 2aaa | Pushes pc onto the stack, then jumps to a + #[opcode = "0x2AAA"] + call { A: u16 }, + /// | 3xbb | Skips next instruction if register X == b + #[opcode = "0x3xBB"] + seb { B: u8, x: usize }, + /// | 4xbb | Skips next instruction if register X != b + #[opcode = "0x4xBB"] + sneb { B: u8, x: usize }, + /// | 9XY0 | Skip next instruction if vX == vY | + #[opcode = "0x5xy0"] + se { y: usize, x: usize }, + /// | 6xbb | Loads immediate byte b into register vX + #[opcode = "0x6xBB"] + movb { B: u8, x: usize }, + /// | 7xbb | Adds immediate byte b to register vX + #[opcode = "0x7xBB"] + addb { B: u8, x: usize }, + /// | 8xy0 | Loads the value of y into x + #[opcode = "0x8xy0"] + mov { x: usize, y: usize }, + /// | 8xy1 | Performs bitwise or of vX and vY, and stores the result in vX + #[opcode = "0x8xy1"] + or { y: usize, x: usize }, + /// | 8xy2 | Performs bitwise and of vX and vY, and stores the result in vX + #[opcode = "0x8xy2"] + and { y: usize, x: usize }, + /// | 8xy3 | Performs bitwise xor of vX and vY, and stores the result in vX + #[opcode = "0x8xy3"] + xor { y: usize, x: usize }, + /// | 8xy4 | Performs addition of vX and vY, and stores the result in vX + #[opcode = "0x8xy4"] + add { y: usize, x: usize }, + /// | 8xy5 | Performs subtraction of vX and vY, and stores the result in vX + #[opcode = "0x8xy5"] + sub { y: usize, x: usize }, + /// | 8xy6 | Performs bitwise right shift of vX (or vY) + #[opcode = "0x8xy6"] + shr { y: usize, x: usize }, + /// | 8xy7 | Performs subtraction of vY and vX, and stores the result in vX + #[opcode = "0x8xy7"] + bsub { y: usize, x: usize }, + /// | 8xyE | Performs bitwise left shift of vX + #[opcode = "0x8xye"] + shl { y: usize, x: usize }, + /// | 9XY0 | Skip next instruction if vX != vY + #[opcode = "0x9xy0"] + sne { y: usize, x: usize }, + /// | Aaaa | Load address #a into register I + #[opcode = "0xaAAA"] + movI { A: usize }, + /// | Baaa | Jump to &adr + v0 + #[opcode = "0xbAAA"] + jmpr { A: usize }, + /// | Cxbb | Stores a random number & the provided byte into vX + #[opcode = "0xcxBB"] + rand { B: u8, x: usize }, + /// | Dxyn | Draws n-byte sprite to the screen at coordinates (vX, vY) + #[opcode = "0xdxyn"] + draw { x: usize, y: usize, n: u8 }, + /// | eX9e | Skip next instruction if key == vX + #[opcode = "0xex9e"] + sek { x: usize }, + /// | eXa1 | Skip next instruction if key != vX + #[opcode = "0xexa1"] + snek { x: usize }, + // | fX07 | Set vX to value in delay timer + #[opcode = "0xfx07"] + getdt { x: usize }, + // | fX0a | Wait for input, store key in vX + #[opcode = "0xfx0a"] + waitk { x: usize }, + // | fX15 | Set sound timer to the value in vX + #[opcode = "0xfx15"] + setdt { x: usize }, + // | fX18 | set delay timer to the value in vX + #[opcode = "0xfx18"] + movst { x: usize }, + // | fX1e | Add vX to I + #[opcode = "0xfx1e"] + addI { x: usize }, + // | fX29 | Load sprite for character x into I + #[opcode = "0xfx29"] + font { x: usize }, + // | fX33 | BCD convert X into I[0..3] + #[opcode = "0xfx33"] + bcd { x: usize }, + // | fX55 | DMA Stor from I to registers 0..X + #[opcode = "0xfx55"] + dmao { x: usize }, + // | fX65 | DMA Load from I to registers 0..X + #[opcode = "0xfx65"] + dmai { x: usize }, +} + +impl Display for Insn { + #[rustfmt::skip] + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + match self { + Insn::cls => write!(f, "cls "), + Insn::ret => write!(f, "ret "), + Insn::jmp { A } => write!(f, "jmp {A:03x}"), + Insn::call { A } => write!(f, "call {A:03x}"), + Insn::seb { B, x } => write!(f, "se #{B:02x}, v{x:X}"), + Insn::sneb { B, x } => write!(f, "sne #{B:02x}, v{x:X}"), + Insn::se { y, x } => write!(f, "se v{x:X}, v{y:X}"), + Insn::movb { B, x } => write!(f, "mov #{B:02x}, v{x:X}"), + Insn::addb { B, x } => write!(f, "add #{B:02x}, v{x:X}"), + Insn::mov { x, y } => write!(f, "mov v{y:X}, v{x:X}"), + Insn::or { y, x } => write!(f, "or v{y:X}, v{x:X}"), + Insn::and { y, x } => write!(f, "and v{y:X}, v{x:X}"), + Insn::xor { y, x } => write!(f, "xor v{y:X}, v{x:X}"), + Insn::add { y, x } => write!(f, "add v{y:X}, v{x:X}"), + Insn::sub { y, x } => write!(f, "sub v{y:X}, v{x:X}"), + Insn::shr { y, x } => write!(f, "shr v{y:X}, v{x:X}"), + Insn::bsub { y, x } => write!(f, "bsub v{y:X}, v{x:X}"), + Insn::shl { y, x } => write!(f, "shl v{y:X}, v{x:X}"), + Insn::sne { y, x } => write!(f, "sne v{x:X}, v{y:X}"), + Insn::movI { A } => write!(f, "mov ${A:03x}, I"), + Insn::jmpr { A } => write!(f, "jmp ${A:03x}+v0"), + Insn::rand { B, x } => write!(f, "rand #{B:02x}, v{x:X}"), + Insn::draw { x, y, n } => write!(f, "draw #{n:x}, v{x:X}, v{y:X}"), + Insn::sek { x } => write!(f, "sek v{x:X}"), + Insn::snek { x } => write!(f, "snek v{x:X}"), + Insn::getdt { x } => write!(f, "mov DT, v{x:X}"), + Insn::waitk { x } => write!(f, "waitk v{x:X}"), + Insn::setdt { x } => write!(f, "mov v{x:X}, DT"), + Insn::movst { x } => write!(f, "mov v{x:X}, ST"), + Insn::addI { x } => write!(f, "add v{x:X}, I"), + Insn::font { x } => write!(f, "font v{x:X}, I"), + Insn::bcd { x } => write!(f, "bcd v{x:X}, &I"), + Insn::dmao { x } => write!(f, "dmao v{x:X}"), + Insn::dmai { x } => write!(f, "dmai v{x:X}"), + } + } +} + +/// Disassembles Chip-8 instructions, printing them in the provided [owo_colors::Style]s +#[derive(Clone, Copy, Debug, PartialEq)] +pub struct Dis { + /// Styles invalid instructions + pub invalid: Style, + /// Styles valid instruction + pub normal: Style, +} + +impl Default for Dis { + fn default() -> Self { + Self { + invalid: Style::new().bold().red(), + normal: Style::new().green(), + } + } +} + +impl Disassembler for Dis { + fn once(&self, insn: u16) -> String { + if let Some((_, insn)) = Insn::decode(&insn.to_be_bytes()).ok() { + format!("{}", insn.style(self.normal)) + } else { + format!("{}", format_args!("inval {insn:04x}").style(self.invalid)) + } + } +} diff --git a/src/cpu/disassemble.rs b/src/cpu/old_disassembler.rs similarity index 96% rename from src/cpu/disassemble.rs rename to src/cpu/old_disassembler.rs index 3322195..8d9e9bf 100644 --- a/src/cpu/disassemble.rs +++ b/src/cpu/old_disassembler.rs @@ -3,7 +3,7 @@ //! A disassembler for Chip-8 opcodes -use super::{Adr, Nib, Reg}; +use super::{Adr, Disassembler, Nib, Reg}; use owo_colors::{OwoColorize, Style}; type Ins = Nib; @@ -40,22 +40,22 @@ pub fn a(ins: u16) -> Adr { /// Disassembles Chip-8 instructions, printing them in the provided [owo_colors::Style]s #[derive(Clone, Debug, PartialEq)] -pub struct Disassemble { +pub struct DeprecatedDisassembler { invalid: Style, normal: Style, } -impl Default for Disassemble { +impl Default for DeprecatedDisassembler { fn default() -> Self { - Disassemble::builder().build() + DeprecatedDisassembler::builder().build() } } // Public API -impl Disassemble { +impl DeprecatedDisassembler { /// Returns a new Disassemble with the provided Styles - pub fn new(invalid: Style, normal: Style) -> Disassemble { - Disassemble { invalid, normal } + pub fn new(invalid: Style, normal: Style) -> DeprecatedDisassembler { + DeprecatedDisassembler { invalid, normal } } /// Creates a [DisassembleBuilder], for partial configuration pub fn builder() -> DisassembleBuilder { @@ -183,8 +183,14 @@ impl Disassemble { } } +impl Disassembler for DeprecatedDisassembler { + fn once(&self, insn: u16) -> String { + self.instruction(insn) + } +} + // Private api -impl Disassemble { +impl DeprecatedDisassembler { /// Unused instructions fn unimplemented(&self, opcode: u16) -> String { format!("inval {opcode:04x}") @@ -400,8 +406,8 @@ impl DisassembleBuilder { self } /// Builds a Disassemble - pub fn build(self) -> Disassemble { - Disassemble { + pub fn build(self) -> DeprecatedDisassembler { + DeprecatedDisassembler { invalid: if let Some(style) = self.invalid { style } else { diff --git a/src/lib.rs b/src/lib.rs index f2cd5f3..667e5c8 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -19,7 +19,7 @@ pub mod prelude { use super::*; pub use crate::bus; pub use bus::{Bus, Read, Region::*, Write}; - pub use cpu::{disassemble::Disassemble, ControlFlags, CPU}; + pub use cpu::{disassembler::Dis, ControlFlags, CPU}; pub use error::Result; pub use io::{UIBuilder, *}; } From 8ab979991308d687352b4800ad3ac3e9a0e5175b Mon Sep 17 00:00:00 2001 From: John Breaux Date: Thu, 30 Mar 2023 02:13:59 -0500 Subject: [PATCH 2/6] cpu.rs: Fix some documentation errors --- src/cpu.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/cpu.rs b/src/cpu.rs index 3f3744d..0c6b217 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -1032,7 +1032,7 @@ impl CPU { } } -// | Cxbb | Stores a random number + the provided byte into vX +// | Cxbb | Stores a random number & the provided byte into vX impl CPU { /// Cxbb: Stores a random number & the provided byte into vX #[inline] @@ -1080,10 +1080,10 @@ impl CPU { // // |opcode| effect | // |------|------------------------------------| -// | eX9e | Skip next instruction if key == #X | -// | eXa1 | Skip next instruction if key != #X | +// | eX9e | Skip next instruction if key == vX | +// | eXa1 | Skip next instruction if key != vX | impl CPU { - /// Ex9E: Skip next instruction if key == #X + /// Ex9E: Skip next instruction if key == vX #[inline] fn skip_key_equals(&mut self, x: Reg) { let x = self.v[x] as usize; @@ -1091,7 +1091,7 @@ impl CPU { self.pc += 2; } } - /// ExaE: Skip next instruction if key != #X + /// ExaE: Skip next instruction if key != vX #[inline] fn skip_key_not_equals(&mut self, x: Reg) { let x = self.v[x] as usize; @@ -1106,14 +1106,14 @@ impl CPU { // |opcode| effect | // |------|------------------------------------| // | fX07 | Set vX to value in delay timer | -// | fX0a | Wait for input, store in vX m | +// | fX0a | Wait for input, store key in vX | // | fX15 | Set sound timer to the value in vX | // | fX18 | set delay timer to the value in vX | -// | fX1e | Add x to I | +// | fX1e | Add vX to I | // | fX29 | Load sprite for character x into I | // | fX33 | BCD convert X into I[0..3] | -// | fX55 | DMA Stor from I to registers 0..X | -// | fX65 | DMA Load from I to registers 0..X | +// | fX55 | DMA Stor from I to registers 0..=X | +// | fX65 | DMA Load from I to registers 0..=X | impl CPU { /// Fx07: Get the current DT, and put it in vX /// ```py @@ -1174,7 +1174,7 @@ impl CPU { bus.write(self.i.wrapping_add(1), x / 10 % 10); bus.write(self.i, x / 100 % 10); } - /// Fx55: DMA Stor from I to registers 0..X + /// Fx55: DMA Stor from I to registers 0..=X /// /// # Quirk /// The original chip-8 interpreter uses I to directly index memory, @@ -1194,7 +1194,7 @@ impl CPU { self.i += x as Adr + 1; } } - /// Fx65: DMA Load from I to registers 0..X + /// Fx65: DMA Load from I to registers 0..=X /// /// # Quirk /// The original chip-8 interpreter uses I to directly index memory, From cc3bc3a7fe716f0fd98da73b304d222c4097258c Mon Sep 17 00:00:00 2001 From: John Breaux Date: Thu, 30 Mar 2023 08:27:06 -0500 Subject: [PATCH 3/6] Major Refactor: Make invalid states unrepresentable:tm: - Rewrote the instruction decoder as an enum - Used imperative_rs to auto-generate the bit twiddling logic - Implemented Display on that enum, for disassembly - Rewrote CPU::tick - Now >10x faster - Disassembly mode is still 5x slower though - Implemented time-based benchmarking - (use option -S to set the number of instructions per epoch) --- justfile | 2 +- src/bin/chirp-minifb.rs | 25 ++- src/cpu.rs | 339 ++++++++++++----------------- src/cpu/disassembler.rs | 6 +- src/cpu/old_disassembler.rs | 423 ------------------------------------ src/cpu/tests.rs | 32 +-- src/cpu/tests/decode.rs | 2 +- src/error.rs | 11 + src/io.rs | 17 +- tests/chip8_test_suite.rs | 2 +- tests/integration.rs | 2 +- 11 files changed, 200 insertions(+), 661 deletions(-) delete mode 100644 src/cpu/old_disassembler.rs diff --git a/justfile b/justfile index 910a56c..0835fd7 100644 --- a/justfile +++ b/justfile @@ -4,7 +4,7 @@ test: cargo test --doc && cargo nextest run chirp: - cargo run --bin chirp -- tests/chip8-test-suite/bin/chip8-test-suite.ch8 + cargo run --bin chirp-minifb -- tests/chip8-test-suite/bin/chip8-test-suite.ch8 cover: cargo llvm-cov --open --doctests diff --git a/src/bin/chirp-minifb.rs b/src/bin/chirp-minifb.rs index 3ba905e..e31f17b 100644 --- a/src/bin/chirp-minifb.rs +++ b/src/bin/chirp-minifb.rs @@ -127,27 +127,36 @@ impl State { state.ch8.bus.write(0x1feu16, options.data); Ok(state) } - fn keys(&mut self) -> Option<()> { + fn keys(&mut self) -> Result> { self.ui.keys(&mut self.ch8) } fn frame(&mut self) -> Option<()> { self.ui.frame(&mut self.ch8) } - fn tick_cpu(&mut self) { + fn tick_cpu(&mut self) -> Result<()> { if !self.ch8.cpu.flags.pause { let rate = self.speed; match self.step { Some(ticks) => { - self.ch8.cpu.multistep(&mut self.ch8.bus, ticks); + let time = Instant::now(); + self.ch8.cpu.multistep(&mut self.ch8.bus, ticks)?; + let time = time.elapsed(); + let nspt = time.as_secs_f64() / ticks as f64; + eprintln!( + "{ticks},\t{time:.05?},\t{:.4}nspt,\t{}ipf", + nspt * 1_000_000_000.0, + ((1.0 / 60.0f64) / nspt).trunc(), + ); // Pause the CPU and clear step - self.ch8.cpu.flags.pause = true; - self.step = None; + //self.ch8.cpu.flags.pause = true; + //self.step = None; } None => { - self.ch8.cpu.multistep(&mut self.ch8.bus, rate); + self.ch8.cpu.multistep(&mut self.ch8.bus, rate)?; } } } + Ok(()) } fn wait_for_next_frame(&mut self) { let rate = 1_000_000_000 / self.rate + 1; @@ -161,8 +170,8 @@ impl Iterator for State { fn next(&mut self) -> Option { self.wait_for_next_frame(); - self.keys()?; - self.tick_cpu(); + self.keys().unwrap_or_else(|_| None)?; + self.tick_cpu().ok()?; self.frame(); Some(()) } diff --git a/src/cpu.rs b/src/cpu.rs index 0c6b217..353d8d4 100644 --- a/src/cpu.rs +++ b/src/cpu.rs @@ -13,10 +13,13 @@ pub trait Disassembler { } pub mod disassembler; -pub mod old_disassembler; -use self::disassembler::Dis; -use crate::bus::{Bus, Read, Region, Write}; +use self::disassembler::{Dis, Insn}; +use crate::{ + bus::{Bus, Read, Region, Write}, + error::Result, +}; +use imperative_rs::InstructionSet; use owo_colors::OwoColorize; use rand::random; use std::time::Instant; @@ -123,6 +126,22 @@ impl ControlFlags { } } +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +struct Timers { + frame: Instant, + insn: Instant, +} + +impl Default for Timers { + fn default() -> Self { + let now = Instant::now(); + Self { + frame: now, + insn: now, + } + } +} + /// Represents the internal state of the CPU interpreter #[derive(Clone, Debug, PartialEq)] pub struct CPU { @@ -142,7 +161,7 @@ pub struct CPU { // I/O keys: [bool; 16], // Execution data - timer: Instant, + timers: Timers, cycle: usize, breakpoints: Vec, disassembler: Dis, @@ -160,7 +179,7 @@ impl CPU { /// 0x50, // font location /// 0x200, // start of program /// 0xefe, // top of stack - /// Disassemble::default(), + /// Dis::default(), /// vec![], // Breakpoints /// ControlFlags::default() /// ); @@ -343,7 +362,7 @@ impl CPU { /// 0x50, /// 0x340, /// 0xefe, - /// Disassemble::default(), + /// Dis::default(), /// vec![], /// ControlFlags::default() /// ); @@ -419,18 +438,18 @@ impl CPU { /// ], /// Screen [0x0f00..0x1000], /// }; - /// cpu.singlestep(&mut bus); + /// cpu.singlestep(&mut bus)?; /// assert_eq!(0x202, cpu.pc()); /// assert_eq!(1, cpu.cycle()); ///# Ok(()) ///# } /// ``` - pub fn singlestep(&mut self, bus: &mut Bus) -> &mut Self { + pub fn singlestep(&mut self, bus: &mut Bus) -> Result<&mut Self> { self.flags.pause = false; - self.tick(bus); + self.tick(bus)?; self.flags.vbi_wait = false; self.flags.pause = true; - self + Ok(self) } /// Unpauses the emulator for `steps` ticks @@ -448,18 +467,18 @@ impl CPU { /// ], /// Screen [0x0f00..0x1000], /// }; - /// cpu.multistep(&mut bus, 0x20); + /// cpu.multistep(&mut bus, 0x20)?; /// assert_eq!(0x202, cpu.pc()); /// assert_eq!(0x20, cpu.cycle()); ///# Ok(()) ///# } /// ``` - pub fn multistep(&mut self, bus: &mut Bus, steps: usize) -> &mut Self { + pub fn multistep(&mut self, bus: &mut Bus, steps: usize) -> Result<&mut Self> { for _ in 0..steps { - self.tick(bus); + self.tick(bus)?; self.vertical_blank(); } - self + Ok(self) } /// Simulates vertical blanking @@ -471,6 +490,7 @@ impl CPU { /// - Subtracts the elapsed time in fractions of a frame /// from st/dt /// - Disables framepause if the duration exceeds that of a frame + #[inline(always)] pub fn vertical_blank(&mut self) -> &mut Self { if self.flags.pause { return self; @@ -480,14 +500,15 @@ impl CPU { if self.flags.vbi_wait { self.flags.vbi_wait = !(self.cycle % speed == 0); } - self.delay -= 1.0 / speed as f64; - self.sound -= 1.0 / speed as f64; + let speed = 1.0 / speed as f64; + self.delay -= speed; + self.sound -= speed; return self; }; // Convert the elapsed time to 60ths of a second - let time = self.timer.elapsed().as_secs_f64() * 60.0; - self.timer = Instant::now(); + let time = self.timers.frame.elapsed().as_secs_f64() * 60.0; + self.timers.frame = Instant::now(); if time > 1.0 { self.flags.vbi_wait = false; } @@ -513,7 +534,7 @@ impl CPU { /// ], /// Screen [0x0f00..0x1000], /// }; - /// cpu.tick(&mut bus); + /// cpu.tick(&mut bus)?; /// assert_eq!(0x202, cpu.pc()); /// assert_eq!(1, cpu.cycle()); ///# Ok(()) @@ -534,162 +555,93 @@ impl CPU { /// ], /// Screen [0x0f00..0x1000], /// }; - /// cpu.multistep(&mut bus, 0x10); // panics! + /// cpu.tick(&mut bus)?; // panics! ///# Ok(()) ///# } /// ``` - pub fn tick(&mut self, bus: &mut Bus) -> &mut Self { + pub fn tick(&mut self, bus: &mut Bus) -> Result<&mut Self> { // Do nothing if paused if self.flags.pause || self.flags.vbi_wait || self.flags.keypause { // always tick in test mode if self.flags.monotonic.is_some() { self.cycle += 1; } - return self; + return Ok(self); } self.cycle += 1; // fetch opcode - let opcode: u16 = bus.read(self.pc); - let pc = self.pc; + let opcode: &[u8; 2] = if let Some(slice) = bus.get(self.pc as usize..self.pc as usize + 2) + { + slice.try_into()? + } else { + return Err(crate::error::Error::InvalidBusRange { + range: self.pc as usize..self.pc as usize + 2, + }); + }; - // DINC pc - self.pc = self.pc.wrapping_add(2); - // decode opcode - - use old_disassembler::{a, b, i, n, x, y}; - let (i, x, y, n, b, a) = ( - i(opcode), - x(opcode), - y(opcode), - n(opcode), - b(opcode), - a(opcode), - ); - match i { - // # Issue a system call - // |opcode| effect | - // |------|------------------------------------| - // | 00e0 | Clear screen memory to all 0 | - // | 00ee | Return from subroutine | - 0x0 => match a { - 0x0e0 => self.clear_screen(bus), - 0x0ee => self.ret(bus), - _ => self.sys(a), - }, - // | 1aaa | Sets pc to an absolute address - 0x1 => self.jump(a), - // | 2aaa | Pushes pc onto the stack, then jumps to a - 0x2 => self.call(a, bus), - // | 3xbb | Skips next instruction if register X == b - 0x3 => self.skip_equals_immediate(x, b), - // | 4xbb | Skips next instruction if register X != b - 0x4 => self.skip_not_equals_immediate(x, b), - // # Performs a register-register comparison - // |opcode| effect | - // |------|------------------------------------| - // | 9XY0 | Skip next instruction if vX == vY | - 0x5 => match n { - 0x0 => self.skip_equals(x, y), - _ => self.unimplemented(opcode), - }, - // 6xbb: Loads immediate byte b into register vX - 0x6 => self.load_immediate(x, b), - // 7xbb: Adds immediate byte b to register vX - 0x7 => self.add_immediate(x, b), - // # Performs ALU operation - // |opcode| effect | - // |------|------------------------------------| - // | 8xy0 | Y = X | - // | 8xy1 | X = X | Y | - // | 8xy2 | X = X & Y | - // | 8xy3 | X = X ^ Y | - // | 8xy4 | X = X + Y; Set vF=carry | - // | 8xy5 | X = X - Y; Set vF=carry | - // | 8xy6 | X = X >> 1 | - // | 8xy7 | X = Y - X; Set vF=carry | - // | 8xyE | X = X << 1 | - 0x8 => match n { - 0x0 => self.load(x, y), - 0x1 => self.or(x, y), - 0x2 => self.and(x, y), - 0x3 => self.xor(x, y), - 0x4 => self.add(x, y), - 0x5 => self.sub(x, y), - 0x6 => self.shift_right(x, y), - 0x7 => self.backwards_sub(x, y), - 0xE => self.shift_left(x, y), - _ => self.unimplemented(opcode), - }, - // # Performs a register-register comparison - // |opcode| effect | - // |------|------------------------------------| - // | 9XY0 | Skip next instruction if vX != vY | - 0x9 => match n { - 0 => self.skip_not_equals(x, y), - _ => self.unimplemented(opcode), - }, - // Aaaa: Load address #a into register I - 0xa => self.load_i_immediate(a), - // Baaa: Jump to &adr + v0 - 0xb => self.jump_indexed(a), - // Cxbb: Stores a random number + the provided byte into vX - 0xc => self.rand(x, b), - // Dxyn: Draws n-byte sprite to the screen at coordinates (vX, vY) - 0xd => self.draw(x, y, n, bus), - - // # Skips instruction on value of keypress - // |opcode| effect | - // |------|------------------------------------| - // | eX9e | Skip next instruction if key == vX | - // | eXa1 | Skip next instruction if key != vX | - 0xe => match b { - 0x9e => self.skip_key_equals(x), - 0xa1 => self.skip_key_not_equals(x), - _ => self.unimplemented(opcode), - }, - - // # Performs IO - // |opcode| effect | - // |------|------------------------------------| - // | fX07 | Set vX to value in delay timer | - // | fX0a | Wait for input, store in vX m | - // | fX15 | Set sound timer to the value in vX | - // | fX18 | set delay timer to the value in vX | - // | fX1e | Add x to I | - // | fX29 | Load sprite for character x into I | - // | fX33 | BCD convert X into I[0..3] | - // | fX55 | DMA Stor from I to registers 0..X | - // | fX65 | DMA Load from I to registers 0..X | - 0xf => match b { - 0x07 => self.load_delay_timer(x), - 0x0A => self.wait_for_key(x), - 0x15 => self.store_delay_timer(x), - 0x18 => self.store_sound_timer(x), - 0x1E => self.add_i(x), - 0x29 => self.load_sprite(x), - 0x33 => self.bcd_convert(x, bus), - 0x55 => self.store_dma(x, bus), - 0x65 => self.load_dma(x, bus), - _ => self.unimplemented(opcode), - }, - _ => unreachable!("Extracted nibble from byte, got >nibble?"), - } - let elapsed = self.timer.elapsed(); // Print opcode disassembly: + if self.flags.debug { - std::println!( - "{:3} {:03x}: {:<36}{:?}", + println!("{:?}", self.timers.insn.elapsed().bright_black()); + self.timers.insn = Instant::now(); + std::print!( + "{:3} {:03x}: {:<36}", self.cycle.bright_black(), - pc, - self.disassembler.once(opcode), - elapsed.dimmed() + self.pc, + self.disassembler.once(u16::from_be_bytes(*opcode)) ); } + + // decode opcode + if let Ok((inc, insn)) = Insn::decode(opcode) { + self.pc = self.pc.wrapping_add(inc as u16); + match insn { + Insn::cls => self.clear_screen(bus), + Insn::ret => self.ret(bus), + Insn::jmp { A } => self.jump(A), + Insn::call { A } => self.call(A, bus), + Insn::seb { B, x } => self.skip_equals_immediate(x, B), + Insn::sneb { B, x } => self.skip_not_equals_immediate(x, B), + Insn::se { y, x } => self.skip_equals(x, y), + Insn::movb { B, x } => self.load_immediate(x, B), + Insn::addb { B, x } => self.add_immediate(x, B), + Insn::mov { x, y } => self.load(x, y), + Insn::or { y, x } => self.or(x, y), + Insn::and { y, x } => self.and(x, y), + Insn::xor { y, x } => self.xor(x, y), + Insn::add { y, x } => self.add(x, y), + Insn::sub { y, x } => self.sub(x, y), + Insn::shr { y, x } => self.shift_right(x, y), + Insn::bsub { y, x } => self.backwards_sub(x, y), + Insn::shl { y, x } => self.shift_left(x, y), + Insn::sne { y, x } => self.skip_not_equals(x, y), + Insn::movI { A } => self.load_i_immediate(A), + Insn::jmpr { A } => self.jump_indexed(A), + Insn::rand { B, x } => self.rand(x, B), + Insn::draw { x, y, n } => self.draw(x, y, n, bus), + Insn::sek { x } => self.skip_key_equals(x), + Insn::snek { x } => self.skip_key_not_equals(x), + Insn::getdt { x } => self.load_delay_timer(x), + Insn::waitk { x } => self.wait_for_key(x), + Insn::setdt { x } => self.store_delay_timer(x), + Insn::movst { x } => self.store_sound_timer(x), + Insn::addI { x } => self.add_i(x), + Insn::font { x } => self.load_sprite(x), + Insn::bcd { x } => self.bcd_convert(x, bus), + Insn::dmao { x } => self.store_dma(x, bus), + Insn::dmai { x } => self.load_dma(x, bus), + } + } else { + return Err(crate::error::Error::UnimplementedInstruction { + word: u16::from_be_bytes(*opcode), + }); + } + // process breakpoints - if self.breakpoints.contains(&self.pc) { + if !self.breakpoints.is_empty() && self.breakpoints.contains(&self.pc) { self.flags.pause = true; } - self + Ok(self) } /// Dumps the current state of all CPU registers, and the cycle count @@ -770,7 +722,7 @@ impl Default for CPU { debug: true, ..Default::default() }, - timer: Instant::now(), + timers: Default::default(), breakpoints: vec![], disassembler: Dis::default(), } @@ -787,18 +739,8 @@ impl Default for CPU { // | 00e0 | Clear screen memory to all 0 | // | 00ee | Return from subroutine | impl CPU { - /// Unused instructions - #[inline] - fn unimplemented(&self, opcode: u16) { - unimplemented!("Opcode: {opcode:04x}") - } - /// 0aaa: Handles a "machine language function call" (lmao) - #[inline] - fn sys(&mut self, a: Adr) { - unimplemented!("SYS\t{a:03x}"); - } /// 00e0: Clears the screen memory to 0 - #[inline] + #[inline(always)] fn clear_screen(&mut self, bus: &mut Bus) { if let Some(screen) = bus.get_region_mut(Region::Screen) { for byte in screen { @@ -807,7 +749,7 @@ impl CPU { } } /// 00ee: Returns from subroutine - #[inline] + #[inline(always)] fn ret(&mut self, bus: &impl Read) { self.sp = self.sp.wrapping_add(2); self.pc = bus.read(self.sp); @@ -817,7 +759,7 @@ impl CPU { // | 1aaa | Sets pc to an absolute address impl CPU { /// 1aaa: Sets the program counter to an absolute address - #[inline] + #[inline(always)] fn jump(&mut self, a: Adr) { // jump to self == halt if a.wrapping_add(2) == self.pc { @@ -830,7 +772,7 @@ impl CPU { // | 2aaa | Pushes pc onto the stack, then jumps to a impl CPU { /// 2aaa: Pushes pc onto the stack, then jumps to a - #[inline] + #[inline(always)] fn call(&mut self, a: Adr, bus: &mut impl Write) { bus.write(self.sp, self.pc); self.sp = self.sp.wrapping_sub(2); @@ -841,7 +783,7 @@ impl CPU { // | 3xbb | Skips next instruction if register X == b impl CPU { /// 3xbb: Skips the next instruction if register X == b - #[inline] + #[inline(always)] fn skip_equals_immediate(&mut self, x: Reg, b: u8) { if self.v[x] == b { self.pc = self.pc.wrapping_add(2); @@ -852,7 +794,7 @@ impl CPU { // | 4xbb | Skips next instruction if register X != b impl CPU { /// 4xbb: Skips the next instruction if register X != b - #[inline] + #[inline(always)] fn skip_not_equals_immediate(&mut self, x: Reg, b: u8) { if self.v[x] != b { self.pc = self.pc.wrapping_add(2); @@ -867,7 +809,7 @@ impl CPU { // | 5XY0 | Skip next instruction if vX == vY | impl CPU { /// 5xy0: Skips the next instruction if register X != register Y - #[inline] + #[inline(always)] fn skip_equals(&mut self, x: Reg, y: Reg) { if self.v[x] == self.v[y] { self.pc = self.pc.wrapping_add(2); @@ -878,7 +820,7 @@ impl CPU { // | 6xbb | Loads immediate byte b into register vX impl CPU { /// 6xbb: Loads immediate byte b into register vX - #[inline] + #[inline(always)] fn load_immediate(&mut self, x: Reg, b: u8) { self.v[x] = b; } @@ -887,7 +829,7 @@ impl CPU { // | 7xbb | Adds immediate byte b to register vX impl CPU { /// 7xbb: Adds immediate byte b to register vX - #[inline] + #[inline(always)] fn add_immediate(&mut self, x: Reg, b: u8) { self.v[x] = self.v[x].wrapping_add(b); } @@ -908,7 +850,7 @@ impl CPU { // | 8xyE | X = X << 1 | impl CPU { /// 8xy0: Loads the value of y into x - #[inline] + #[inline(always)] fn load(&mut self, x: Reg, y: Reg) { self.v[x] = self.v[y]; } @@ -916,7 +858,7 @@ impl CPU { /// /// # Quirk /// The original chip-8 interpreter will clobber vF for any 8-series instruction - #[inline] + #[inline(always)] fn or(&mut self, x: Reg, y: Reg) { self.v[x] |= self.v[y]; if self.flags.quirks.bin_ops { @@ -927,7 +869,7 @@ impl CPU { /// /// # Quirk /// The original chip-8 interpreter will clobber vF for any 8-series instruction - #[inline] + #[inline(always)] fn and(&mut self, x: Reg, y: Reg) { self.v[x] &= self.v[y]; if self.flags.quirks.bin_ops { @@ -938,7 +880,7 @@ impl CPU { /// /// # Quirk /// The original chip-8 interpreter will clobber vF for any 8-series instruction - #[inline] + #[inline(always)] fn xor(&mut self, x: Reg, y: Reg) { self.v[x] ^= self.v[y]; if self.flags.quirks.bin_ops { @@ -946,14 +888,14 @@ impl CPU { } } /// 8xy4: Performs addition of vX and vY, and stores the result in vX - #[inline] + #[inline(always)] fn add(&mut self, x: Reg, y: Reg) { let carry; (self.v[x], carry) = self.v[x].overflowing_add(self.v[y]); self.v[0xf] = carry.into(); } /// 8xy5: Performs subtraction of vX and vY, and stores the result in vX - #[inline] + #[inline(always)] fn sub(&mut self, x: Reg, y: Reg) { let carry; (self.v[x], carry) = self.v[x].overflowing_sub(self.v[y]); @@ -963,7 +905,7 @@ impl CPU { /// /// # Quirk /// On the original chip-8 interpreter, this shifts vY and stores the result in vX - #[inline] + #[inline(always)] fn shift_right(&mut self, x: Reg, y: Reg) { let src: Reg = if self.flags.quirks.shift { y } else { x }; let shift_out = self.v[src] & 1; @@ -971,7 +913,7 @@ impl CPU { self.v[0xf] = shift_out; } /// 8xy7: Performs subtraction of vY and vX, and stores the result in vX - #[inline] + #[inline(always)] fn backwards_sub(&mut self, x: Reg, y: Reg) { let carry; (self.v[x], carry) = self.v[y].overflowing_sub(self.v[x]); @@ -982,7 +924,7 @@ impl CPU { /// # Quirk /// On the original chip-8 interpreter, this would perform the operation on vY /// and store the result in vX. This behavior was left out, for now. - #[inline] + #[inline(always)] fn shift_left(&mut self, x: Reg, y: Reg) { let src: Reg = if self.flags.quirks.shift { y } else { x }; let shift_out: u8 = self.v[src] >> 7; @@ -998,7 +940,7 @@ impl CPU { // | 9XY0 | Skip next instruction if vX != vY | impl CPU { /// 9xy0: Skip next instruction if X != y - #[inline] + #[inline(always)] fn skip_not_equals(&mut self, x: Reg, y: Reg) { if self.v[x] != self.v[y] { self.pc = self.pc.wrapping_add(2); @@ -1009,7 +951,7 @@ impl CPU { // | Aaaa | Load address #a into register I impl CPU { /// Aadr: Load address #adr into register I - #[inline] + #[inline(always)] fn load_i_immediate(&mut self, a: Adr) { self.i = a; } @@ -1021,7 +963,7 @@ impl CPU { /// /// Quirk: /// On the Super-Chip, this does stupid shit - #[inline] + #[inline(always)] fn jump_indexed(&mut self, a: Adr) { let reg = if self.flags.quirks.stupid_jumps { a as usize >> 8 @@ -1035,7 +977,7 @@ impl CPU { // | Cxbb | Stores a random number & the provided byte into vX impl CPU { /// Cxbb: Stores a random number & the provided byte into vX - #[inline] + #[inline(always)] fn rand(&mut self, x: Reg, b: u8) { self.v[x] = random::() & b; } @@ -1047,6 +989,7 @@ impl CPU { /// /// # Quirk /// On the original chip-8 interpreter, this will wait for a VBI + #[inline(always)] fn draw(&mut self, x: Reg, y: Reg, n: Nib, bus: &mut Bus) { let (x, y) = (self.v[x] as u16 % 64, self.v[y] as u16 % 32); if self.flags.quirks.draw_wait { @@ -1084,7 +1027,7 @@ impl CPU { // | eXa1 | Skip next instruction if key != vX | impl CPU { /// Ex9E: Skip next instruction if key == vX - #[inline] + #[inline(always)] fn skip_key_equals(&mut self, x: Reg) { let x = self.v[x] as usize; if self.keys[x] { @@ -1092,7 +1035,7 @@ impl CPU { } } /// ExaE: Skip next instruction if key != vX - #[inline] + #[inline(always)] fn skip_key_not_equals(&mut self, x: Reg) { let x = self.v[x] as usize; if !self.keys[x] { @@ -1119,12 +1062,12 @@ impl CPU { /// ```py /// vX = DT /// ``` - #[inline] + #[inline(always)] fn load_delay_timer(&mut self, x: Reg) { self.v[x] = self.delay as u8; } /// Fx0A: Wait for key, then vX = K - #[inline] + #[inline(always)] fn wait_for_key(&mut self, x: Reg) { if let Some(key) = self.flags.lastkey { self.v[x] = key as u8; @@ -1138,7 +1081,7 @@ impl CPU { /// ```py /// DT = vX /// ``` - #[inline] + #[inline(always)] fn store_delay_timer(&mut self, x: Reg) { self.delay = self.v[x] as f64; } @@ -1146,7 +1089,7 @@ impl CPU { /// ```py /// ST = vX; /// ``` - #[inline] + #[inline(always)] fn store_sound_timer(&mut self, x: Reg) { self.sound = self.v[x] as f64; } @@ -1154,7 +1097,7 @@ impl CPU { /// ```py /// I += vX; /// ``` - #[inline] + #[inline(always)] fn add_i(&mut self, x: Reg) { self.i += self.v[x] as u16; } @@ -1162,12 +1105,12 @@ impl CPU { /// ```py /// I = sprite(X); /// ``` - #[inline] + #[inline(always)] fn load_sprite(&mut self, x: Reg) { self.i = self.font + (5 * (self.v[x] as Adr % 0x10)); } /// Fx33: BCD convert X into I`[0..3]` - #[inline] + #[inline(always)] fn bcd_convert(&mut self, x: Reg, bus: &mut Bus) { let x = self.v[x]; bus.write(self.i.wrapping_add(2), x % 10); @@ -1179,7 +1122,7 @@ impl CPU { /// # Quirk /// The original chip-8 interpreter uses I to directly index memory, /// with the side effect of leaving I as I+X+1 after the transfer is done. - #[inline] + #[inline(always)] fn store_dma(&mut self, x: Reg, bus: &mut Bus) { let i = self.i as usize; for (reg, value) in bus @@ -1199,7 +1142,7 @@ impl CPU { /// # Quirk /// The original chip-8 interpreter uses I to directly index memory, /// with the side effect of leaving I as I+X+1 after the transfer is done. - #[inline] + #[inline(always)] fn load_dma(&mut self, x: Reg, bus: &mut Bus) { let i = self.i as usize; for (reg, value) in bus diff --git a/src/cpu/disassembler.rs b/src/cpu/disassembler.rs index b1825f1..3babd28 100644 --- a/src/cpu/disassembler.rs +++ b/src/cpu/disassembler.rs @@ -6,7 +6,7 @@ use owo_colors::{OwoColorize, Style}; use std::fmt::Display; #[allow(non_camel_case_types, non_snake_case, missing_docs)] -#[derive(Clone, Copy, InstructionSet, PartialEq, Eq, PartialOrd, Ord, Hash)] +#[derive(Clone, Copy, InstructionSet)] /// Implements a Disassembler using imperative_rs pub enum Insn { /// | 00e0 | Clear screen memory to 0s @@ -68,10 +68,10 @@ pub enum Insn { sne { y: usize, x: usize }, /// | Aaaa | Load address #a into register I #[opcode = "0xaAAA"] - movI { A: usize }, + movI { A: u16 }, /// | Baaa | Jump to &adr + v0 #[opcode = "0xbAAA"] - jmpr { A: usize }, + jmpr { A: u16 }, /// | Cxbb | Stores a random number & the provided byte into vX #[opcode = "0xcxBB"] rand { B: u8, x: usize }, diff --git a/src/cpu/old_disassembler.rs b/src/cpu/old_disassembler.rs deleted file mode 100644 index 8d9e9bf..0000000 --- a/src/cpu/old_disassembler.rs +++ /dev/null @@ -1,423 +0,0 @@ -// (c) 2023 John A. Breaux -// This code is licensed under MIT license (see LICENSE.txt for details) - -//! A disassembler for Chip-8 opcodes - -use super::{Adr, Disassembler, Nib, Reg}; -use owo_colors::{OwoColorize, Style}; -type Ins = Nib; - -/// Extracts the I nibble of an IXYN instruction -#[inline] -pub fn i(ins: u16) -> Ins { - (ins >> 12 & 0xf) as Ins -} -/// Extracts the X nibble of an IXYN instruction -#[inline] -pub fn x(ins: u16) -> Reg { - (ins >> 8 & 0xf) as Reg -} -/// Extracts the Y nibble of an IXYN instruction -#[inline] -pub fn y(ins: u16) -> Reg { - (ins >> 4 & 0xf) as Reg -} -/// Extracts the N nibble of an IXYN instruction -#[inline] -pub fn n(ins: u16) -> Nib { - (ins & 0xf) as Nib -} -/// Extracts the B byte of an IXBB instruction -#[inline] -pub fn b(ins: u16) -> u8 { - (ins & 0xff) as u8 -} -/// Extracts the ADR trinibble of an IADR instruction -#[inline] -pub fn a(ins: u16) -> Adr { - ins & 0x0fff -} - -/// Disassembles Chip-8 instructions, printing them in the provided [owo_colors::Style]s -#[derive(Clone, Debug, PartialEq)] -pub struct DeprecatedDisassembler { - invalid: Style, - normal: Style, -} - -impl Default for DeprecatedDisassembler { - fn default() -> Self { - DeprecatedDisassembler::builder().build() - } -} - -// Public API -impl DeprecatedDisassembler { - /// Returns a new Disassemble with the provided Styles - pub fn new(invalid: Style, normal: Style) -> DeprecatedDisassembler { - DeprecatedDisassembler { invalid, normal } - } - /// Creates a [DisassembleBuilder], for partial configuration - pub fn builder() -> DisassembleBuilder { - DisassembleBuilder::default() - } - /// Disassemble a single instruction - pub fn instruction(&self, opcode: u16) -> String { - let (i, x, y, n, b, a) = ( - i(opcode), - x(opcode), - y(opcode), - n(opcode), - b(opcode), - a(opcode), - ); - match i { - // # Issue a system call - // |opcode| effect | - // |------|------------------------------------| - // | 00e0 | Clear screen memory to all 0 | - // | 00ee | Return from subroutine | - 0x0 => match a { - 0x0e0 => self.clear_screen(), - 0x0ee => self.ret(), - _ => self.sys(a), - }, - // | 1aaa | Sets pc to an absolute address - 0x1 => self.jump(a), - // | 2aaa | Pushes pc onto the stack, then jumps to a - 0x2 => self.call(a), - // | 3xbb | Skips next instruction if register X == b - 0x3 => self.skip_equals_immediate(x, b), - // | 4xbb | Skips next instruction if register X != b - 0x4 => self.skip_not_equals_immediate(x, b), - // # Performs a register-register comparison - // |opcode| effect | - // |------|------------------------------------| - // | 9XY0 | Skip next instruction if vX == vY | - 0x5 => match n { - 0x0 => self.skip_equals(x, y), - _ => self.unimplemented(opcode), - }, - // 6xbb: Loads immediate byte b into register vX - 0x6 => self.load_immediate(x, b), - // 7xbb: Adds immediate byte b to register vX - 0x7 => self.add_immediate(x, b), - // # Performs ALU operation - // |opcode| effect | - // |------|------------------------------------| - // | 8xy0 | Y = X | - // | 8xy1 | X = X | Y | - // | 8xy2 | X = X & Y | - // | 8xy3 | X = X ^ Y | - // | 8xy4 | X = X + Y; Set vF=carry | - // | 8xy5 | X = X - Y; Set vF=carry | - // | 8xy6 | X = X >> 1 | - // | 8xy7 | X = Y - X; Set vF=carry | - // | 8xyE | X = X << 1 | - 0x8 => match n { - 0x0 => self.load(x, y), - 0x1 => self.or(x, y), - 0x2 => self.and(x, y), - 0x3 => self.xor(x, y), - 0x4 => self.add(x, y), - 0x5 => self.sub(x, y), - 0x6 => self.shift_right(x), - 0x7 => self.backwards_sub(x, y), - 0xE => self.shift_left(x), - _ => self.unimplemented(opcode), - }, - // # Performs a register-register comparison - // |opcode| effect | - // |------|------------------------------------| - // | 9XY0 | Skip next instruction if vX != vY | - 0x9 => match n { - 0 => self.skip_not_equals(x, y), - _ => self.unimplemented(opcode), - }, - // Aaaa: Load address #a into register I - 0xa => self.load_i_immediate(a), - // Baaa: Jump to &adr + v0 - 0xb => self.jump_indexed(a), - // Cxbb: Stores a random number + the provided byte into vX - 0xc => self.rand(x, b), - // Dxyn: Draws n-byte sprite to the screen at coordinates (vX, vY) - 0xd => self.draw(x, y, n), - - // # Skips instruction on value of keypress - // |opcode| effect | - // |------|------------------------------------| - // | eX9e | Skip next instruction if key == #X | - // | eXa1 | Skip next instruction if key != #X | - 0xe => match b { - 0x9e => self.skip_key_equals(x), - 0xa1 => self.skip_key_not_equals(x), - _ => self.unimplemented(opcode), - }, - - // # Performs IO - // |opcode| effect | - // |------|------------------------------------| - // | fX07 | Set vX to value in delay timer | - // | fX0a | Wait for input, store in vX m | - // | fX15 | Set sound timer to the value in vX | - // | fX18 | set delay timer to the value in vX | - // | fX1e | Add x to I | - // | fX29 | Load sprite for character x into I | - // | fX33 | BCD convert X into I[0..3] | - // | fX55 | DMA Stor from I to registers 0..X | - // | fX65 | DMA Load from I to registers 0..X | - 0xf => match b { - 0x07 => self.load_delay_timer(x), - 0x0A => self.wait_for_key(x), - 0x15 => self.store_delay_timer(x), - 0x18 => self.store_sound_timer(x), - 0x1E => self.add_to_indirect(x), - 0x29 => self.load_sprite(x), - 0x33 => self.bcd_convert(x), - 0x55 => self.store_dma(x), - 0x65 => self.load_dma(x), - _ => self.unimplemented(opcode), - }, - _ => unreachable!("Extracted nibble from byte, got >nibble?"), - } - } -} - -impl Disassembler for DeprecatedDisassembler { - fn once(&self, insn: u16) -> String { - self.instruction(insn) - } -} - -// Private api -impl DeprecatedDisassembler { - /// Unused instructions - fn unimplemented(&self, opcode: u16) -> String { - format!("inval {opcode:04x}") - .style(self.invalid) - .to_string() - } - /// `0aaa`: Handles a "machine language function call" (lmao) - pub fn sys(&self, a: Adr) -> String { - format!("sysc {a:03x}").style(self.invalid).to_string() - } - /// `00e0`: Clears the screen memory to 0 - pub fn clear_screen(&self) -> String { - "cls ".style(self.normal).to_string() - } - /// `00ee`: Returns from subroutine - pub fn ret(&self) -> String { - "ret ".style(self.normal).to_string() - } - /// `1aaa`: Sets the program counter to an absolute address - pub fn jump(&self, a: Adr) -> String { - format!("jmp {a:03x}").style(self.normal).to_string() - } - /// `2aaa`: Pushes pc onto the stack, then jumps to a - pub fn call(&self, a: Adr) -> String { - format!("call {a:03x}").style(self.normal).to_string() - } - /// `3xbb`: Skips the next instruction if register X == b - pub fn skip_equals_immediate(&self, x: Reg, b: u8) -> String { - format!("se #{b:02x}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `4xbb`: Skips the next instruction if register X != b - pub fn skip_not_equals_immediate(&self, x: Reg, b: u8) -> String { - format!("sne #{b:02x}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `5xy0`: Skips the next instruction if register X != register Y - pub fn skip_equals(&self, x: Reg, y: Reg) -> String { - format!("se v{x:X}, v{y:X}") - .style(self.normal) - .to_string() - } - - /// `6xbb`: Loads immediate byte b into register vX - pub fn load_immediate(&self, x: Reg, b: u8) -> String { - format!("mov #{b:02x}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `7xbb`: Adds immediate byte b to register vX - pub fn add_immediate(&self, x: Reg, b: u8) -> String { - format!("add #{b:02x}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `8xy0`: Loads the value of y into x - pub fn load(&self, x: Reg, y: Reg) -> String { - format!("mov v{y:X}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `8xy1`: Performs bitwise or of vX and vY, and stores the result in vX - pub fn or(&self, x: Reg, y: Reg) -> String { - format!("or v{y:X}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `8xy2`: Performs bitwise and of vX and vY, and stores the result in vX - pub fn and(&self, x: Reg, y: Reg) -> String { - format!("and v{y:X}, v{x:X}") - .style(self.normal) - .to_string() - } - - /// `8xy3`: Performs bitwise xor of vX and vY, and stores the result in vX - pub fn xor(&self, x: Reg, y: Reg) -> String { - format!("xor v{y:X}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `8xy4`: Performs addition of vX and vY, and stores the result in vX - pub fn add(&self, x: Reg, y: Reg) -> String { - format!("add v{y:X}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `8xy5`: Performs subtraction of vX and vY, and stores the result in vX - pub fn sub(&self, x: Reg, y: Reg) -> String { - format!("sub v{y:X}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `8xy6`: Performs bitwise right shift of vX - pub fn shift_right(&self, x: Reg) -> String { - format!("shr v{x:X}").style(self.normal).to_string() - } - /// `8xy7`: Performs subtraction of vY and vX, and stores the result in vX - pub fn backwards_sub(&self, x: Reg, y: Reg) -> String { - format!("bsub v{y:X}, v{x:X}") - .style(self.normal) - .to_string() - } - /// 8X_E: Performs bitwise left shift of vX - pub fn shift_left(&self, x: Reg) -> String { - format!("shl v{x:X}").style(self.normal).to_string() - } - /// `9xy0`: Skip next instruction if X != y - pub fn skip_not_equals(&self, x: Reg, y: Reg) -> String { - format!("sne v{x:X}, v{y:X}") - .style(self.normal) - .to_string() - } - /// Aadr: Load address #adr into register I - pub fn load_i_immediate(&self, a: Adr) -> String { - format!("mov ${a:03x}, I").style(self.normal).to_string() - } - /// Badr: Jump to &adr + v0 - pub fn jump_indexed(&self, a: Adr) -> String { - format!("jmp ${a:03x}+v0").style(self.normal).to_string() - } - /// `Cxbb`: Stores a random number + the provided byte into vX - /// Pretty sure the input byte is supposed to be the seed of a LFSR or something - pub fn rand(&self, x: Reg, b: u8) -> String { - format!("rand #{b:X}, v{x:X}") - .style(self.normal) - .to_string() - } - /// `Dxyn`: Draws n-byte sprite to the screen at coordinates (vX, vY) - pub fn draw(&self, x: Reg, y: Reg, n: Nib) -> String { - format!("draw #{n:x}, v{x:X}, v{y:X}") - .style(self.normal) - .to_string() - } - /// `Ex9E`: Skip next instruction if key == #X - pub fn skip_key_equals(&self, x: Reg) -> String { - format!("sek v{x:X}").style(self.normal).to_string() - } - /// `ExaE`: Skip next instruction if key != #X - pub fn skip_key_not_equals(&self, x: Reg) -> String { - format!("snek v{x:X}").style(self.normal).to_string() - } - /// `Fx07`: Get the current DT, and put it in vX - /// ```py - /// vX = DT - /// ``` - pub fn load_delay_timer(&self, x: Reg) -> String { - format!("mov DT, v{x:X}").style(self.normal).to_string() - } - /// `Fx0A`: Wait for key, then vX = K - pub fn wait_for_key(&self, x: Reg) -> String { - format!("waitk v{x:X}").style(self.normal).to_string() - } - /// `Fx15`: Load vX into DT - /// ```py - /// DT = vX - /// ``` - pub fn store_delay_timer(&self, x: Reg) -> String { - format!("mov v{x:X}, DT").style(self.normal).to_string() - } - /// `Fx18`: Load vX into ST - /// ```py - /// ST = vX; - /// ``` - pub fn store_sound_timer(&self, x: Reg) -> String { - format!("mov v{x:X}, ST").style(self.normal).to_string() - } - /// `Fx1e`: Add vX to I, - /// ```py - /// I += vX; - /// ``` - pub fn add_to_indirect(&self, x: Reg) -> String { - format!("add v{x:X}, I").style(self.normal).to_string() - } - /// `Fx29`: Load sprite for character in vX into I - /// ```py - /// I = sprite(X); - /// ``` - pub fn load_sprite(&self, x: Reg) -> String { - format!("font v{x:X}, I").style(self.normal).to_string() - } - /// `Fx33`: BCD convert X into I`[0..3]` - pub fn bcd_convert(&self, x: Reg) -> String { - format!("bcd v{x:X}, &I").style(self.normal).to_string() - } - /// `Fx55`: DMA Stor from I to registers 0..X - pub fn store_dma(&self, x: Reg) -> String { - format!("dmao v{x:X}").style(self.normal).to_string() - } - /// `Fx65`: DMA Load from I to registers 0..X - pub fn load_dma(&self, x: Reg) -> String { - format!("dmai v{x:X}").style(self.normal).to_string() - } -} - -/// Builder for [Disassemble]rs -#[derive(Clone, Debug, Default, PartialEq)] -pub struct DisassembleBuilder { - invalid: Option