cpu.rs: Make private function names more concise
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5520d4ab69
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141
src/cpu.rs
141
src/cpu.rs
@ -227,15 +227,15 @@ impl CPU {
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// | 2aaa | Pushes pc onto the stack, then jumps to a
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0x2 => self.call(a, bus),
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// | 3xbb | Skips next instruction if register X == b
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0x3 => self.skip_if_x_equal_byte(x, b),
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0x3 => self.skip_equals_immediate(x, b),
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// | 4xbb | Skips next instruction if register X != b
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0x4 => self.skip_if_x_not_equal_byte(x, b),
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0x4 => self.skip_not_equals_immediate(x, b),
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// # Performs a register-register comparison
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// |opcode| effect |
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// |------|------------------------------------|
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// | 9XY0 | Skip next instruction if vX == vY |
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0x5 => match n {
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0x0 => self.skip_if_x_equal_y(x, y),
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0x0 => self.skip_equals(x, y),
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_ => self.unimplemented(opcode),
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},
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// 6xbb: Loads immediate byte b into register vX
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@ -255,15 +255,15 @@ impl CPU {
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// | 8xy7 | X = Y - X; Set vF=carry |
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// | 8xyE | X = X << 1 |
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0x8 => match n {
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0x0 => self.load_y_into_x(x, y),
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0x1 => self.x_orequals_y(x, y),
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0x2 => self.x_andequals_y(x, y),
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0x3 => self.x_xorequals_y(x, y),
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0x4 => self.x_addequals_y(x, y),
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0x5 => self.x_subequals_y(x, y),
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0x6 => self.shift_right_x(x),
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0x7 => self.backwards_subtract(x, y),
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0xE => self.shift_left_x(x),
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0x0 => self.load(x, y),
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0x1 => self.or(x, y),
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0x2 => self.and(x, y),
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0x3 => self.xor(x, y),
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0x4 => self.add(x, y),
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0x5 => self.sub(x, y),
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0x6 => self.shift_right(x, y),
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0x7 => self.backwards_sub(x, y),
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0xE => self.shift_left(x, y),
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_ => self.unimplemented(opcode),
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},
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// # Performs a register-register comparison
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@ -271,11 +271,11 @@ impl CPU {
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// |------|------------------------------------|
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// | 9XY0 | Skip next instruction if vX != vY |
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0x9 => match n {
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0 => self.skip_if_x_not_equal_y(x, y),
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0 => self.skip_not_equals(x, y),
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_ => self.unimplemented(opcode),
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},
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// Aaaa: Load address #a into register I
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0xa => self.load_indirect_register(a),
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0xa => self.load_i_immediate(a),
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// Baaa: Jump to &adr + v0
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0xb => self.jump_indexed(a),
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// Cxbb: Stores a random number + the provided byte into vX
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@ -286,11 +286,11 @@ impl CPU {
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// # Skips instruction on value of keypress
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// |opcode| effect |
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// |------|------------------------------------|
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// | eX9e | Skip next instruction if key == #X |
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// | eXa1 | Skip next instruction if key != #X |
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// | eX9e | Skip next instruction if key == vX |
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// | eXa1 | Skip next instruction if key != vX |
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0xe => match b {
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0x9e => self.skip_if_key_equals_x(x),
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0xa1 => self.skip_if_key_not_x(x),
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0x9e => self.skip_key_equals(x),
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0xa1 => self.skip_key_not_equals(x),
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_ => self.unimplemented(opcode),
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},
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@ -307,15 +307,15 @@ impl CPU {
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// | fX55 | DMA Stor from I to registers 0..X |
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// | fX65 | DMA Load from I to registers 0..X |
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0xf => match b {
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0x07 => self.get_delay_timer(x),
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0x07 => self.load_delay_timer(x),
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0x0A => self.wait_for_key(x),
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0x15 => self.load_delay_timer(x),
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0x18 => self.load_sound_timer(x),
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0x1E => self.add_to_indirect(x),
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0x29 => self.load_sprite_x(x),
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0x33 => self.bcd_convert_i(x, bus),
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0x55 => self.dma_store(x, bus),
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0x65 => self.dma_load(x, bus),
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0x15 => self.store_delay_timer(x),
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0x18 => self.store_sound_timer(x),
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0x1E => self.add_i(x),
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0x29 => self.load_sprite(x),
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0x33 => self.bcd_convert(x, bus),
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0x55 => self.store_dma(x, bus),
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0x65 => self.load_dma(x, bus),
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_ => self.unimplemented(opcode),
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},
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_ => unimplemented!("Extracted nibble from byte, got >nibble?"),
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@ -398,6 +398,9 @@ impl Default for CPU {
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}
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}
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// Below this point, comments may be duplicated per impl' block,
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// since some opcodes handle multiple instructions.
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// | 0aaa | Issues a "System call" (ML routine)
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//
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// |opcode| effect |
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@ -460,7 +463,7 @@ impl CPU {
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impl CPU {
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/// 3xbb: Skips the next instruction if register X == b
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#[inline]
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fn skip_if_x_equal_byte(&mut self, x: Reg, b: u8) {
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fn skip_equals_immediate(&mut self, x: Reg, b: u8) {
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if self.v[x] == b {
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self.pc = self.pc.wrapping_add(2);
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}
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@ -471,7 +474,7 @@ impl CPU {
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impl CPU {
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/// 4xbb: Skips the next instruction if register X != b
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#[inline]
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fn skip_if_x_not_equal_byte(&mut self, x: Reg, b: u8) {
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fn skip_not_equals_immediate(&mut self, x: Reg, b: u8) {
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if self.v[x] != b {
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self.pc = self.pc.wrapping_add(2);
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}
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@ -486,7 +489,7 @@ impl CPU {
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impl CPU {
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/// 5xy0: Skips the next instruction if register X != register Y
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#[inline]
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fn skip_if_x_equal_y(&mut self, x: Reg, y: Reg) {
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fn skip_equals(&mut self, x: Reg, y: Reg) {
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if self.v[x] == self.v[y] {
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self.pc = self.pc.wrapping_add(2);
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}
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@ -526,32 +529,44 @@ impl CPU {
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// | 8xyE | X = X << 1 |
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impl CPU {
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/// 8xy0: Loads the value of y into x
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///
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/// # Authenticity
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline]
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fn load_y_into_x(&mut self, x: Reg, y: Reg) {
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fn load(&mut self, x: Reg, y: Reg) {
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self.v[x] = self.v[y];
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if self.flags.authentic {
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self.v[0xf] = 0;
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}
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}
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/// 8xy1: Performs bitwise or of vX and vY, and stores the result in vX
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///
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/// # Authenticity
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline]
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fn x_orequals_y(&mut self, x: Reg, y: Reg) {
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fn or(&mut self, x: Reg, y: Reg) {
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self.v[x] |= self.v[y];
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if self.flags.authentic {
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self.v[0xf] = 0;
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}
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}
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/// 8xy2: Performs bitwise and of vX and vY, and stores the result in vX
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///
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/// # Authenticity
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline]
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fn x_andequals_y(&mut self, x: Reg, y: Reg) {
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fn and(&mut self, x: Reg, y: Reg) {
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self.v[x] &= self.v[y];
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if self.flags.authentic {
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self.v[0xf] = 0;
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}
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}
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/// 8xy3: Performs bitwise xor of vX and vY, and stores the result in vX
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///
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/// # Authenticity
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/// The original chip-8 interpreter will clobber vF for any 8-series instruction
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#[inline]
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fn x_xorequals_y(&mut self, x: Reg, y: Reg) {
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fn xor(&mut self, x: Reg, y: Reg) {
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self.v[x] ^= self.v[y];
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if self.flags.authentic {
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self.v[0xf] = 0;
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@ -559,37 +574,47 @@ impl CPU {
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}
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/// 8xy4: Performs addition of vX and vY, and stores the result in vX
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#[inline]
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fn x_addequals_y(&mut self, x: Reg, y: Reg) {
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fn add(&mut self, x: Reg, y: Reg) {
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let carry;
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(self.v[x], carry) = self.v[x].overflowing_add(self.v[y]);
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self.v[0xf] = carry.into();
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}
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/// 8xy5: Performs subtraction of vX and vY, and stores the result in vX
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#[inline]
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fn x_subequals_y(&mut self, x: Reg, y: Reg) {
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fn sub(&mut self, x: Reg, y: Reg) {
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let carry;
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(self.v[x], carry) = self.v[x].overflowing_sub(self.v[y]);
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self.v[0xf] = (!carry).into();
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}
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/// 8xy6: Performs bitwise right shift of vX
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///
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/// # Authenticity
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/// On the original chip-8 interpreter, this would perform the operation on vY
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/// and store the result in vX. This behavior was left out, for now.
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#[inline]
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fn shift_right_x(&mut self, x: Reg) {
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let shift_out = self.v[x] & 1;
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self.v[x] >>= 1;
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fn shift_right(&mut self, x: Reg, y: Reg) {
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let src: Reg = if self.flags.authentic {y} else {x};
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let shift_out = self.v[src] & 1;
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self.v[x] = self.v[src] >> 1;
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self.v[0xf] = shift_out;
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}
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/// 8xy7: Performs subtraction of vY and vX, and stores the result in vX
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#[inline]
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fn backwards_subtract(&mut self, x: Reg, y: Reg) {
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fn backwards_sub(&mut self, x: Reg, y: Reg) {
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let carry;
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(self.v[x], carry) = self.v[y].overflowing_sub(self.v[x]);
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self.v[0xf] = (!carry).into();
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}
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/// 8X_E: Performs bitwise left shift of vX
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///
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/// # Authenticity
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/// On the original chip-8 interpreter, this would perform the operation on vY
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/// and store the result in vX. This behavior was left out, for now.
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#[inline]
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fn shift_left_x(&mut self, x: Reg) {
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let shift_out: u8 = self.v[x] >> 7;
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self.v[x] <<= 1;
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fn shift_left(&mut self, x: Reg, y: Reg) {
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let src: Reg = if self.flags.authentic {y} else {x};
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let shift_out: u8 = self.v[src] >> 7;
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self.v[x] = self.v[src] << 1;
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self.v[0xf] = shift_out;
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}
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}
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@ -602,7 +627,7 @@ impl CPU {
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impl CPU {
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/// 9xy0: Skip next instruction if X != y
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#[inline]
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fn skip_if_x_not_equal_y(&mut self, x: Reg, y: Reg) {
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fn skip_not_equals(&mut self, x: Reg, y: Reg) {
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if self.v[x] != self.v[y] {
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self.pc = self.pc.wrapping_add(2);
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}
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@ -613,7 +638,7 @@ impl CPU {
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impl CPU {
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/// Aadr: Load address #adr into register I
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#[inline]
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fn load_indirect_register(&mut self, a: Adr) {
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fn load_i_immediate(&mut self, a: Adr) {
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self.i = a;
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}
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}
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@ -675,7 +700,7 @@ impl CPU {
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impl CPU {
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/// Ex9E: Skip next instruction if key == #X
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#[inline]
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fn skip_if_key_equals_x(&mut self, x: Reg) {
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fn skip_key_equals(&mut self, x: Reg) {
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let x = self.v[x] as usize;
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if self.keys[x] {
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self.pc += 2;
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@ -683,7 +708,7 @@ impl CPU {
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}
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/// ExaE: Skip next instruction if key != #X
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#[inline]
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fn skip_if_key_not_x(&mut self, x: Reg) {
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fn skip_key_not_equals(&mut self, x: Reg) {
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let x = self.v[x] as usize;
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if !self.keys[x] {
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self.pc += 2;
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@ -710,7 +735,7 @@ impl CPU {
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/// vX = DT
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/// ```
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#[inline]
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fn get_delay_timer(&mut self, x: Reg) {
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fn load_delay_timer(&mut self, x: Reg) {
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self.v[x] = self.delay;
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}
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/// Fx0A: Wait for key, then vX = K
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@ -733,7 +758,7 @@ impl CPU {
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/// DT = vX
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/// ```
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#[inline]
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fn load_delay_timer(&mut self, x: Reg) {
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fn store_delay_timer(&mut self, x: Reg) {
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self.delay = self.v[x];
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}
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/// Fx18: Load vX into ST
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@ -741,7 +766,7 @@ impl CPU {
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/// ST = vX;
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/// ```
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#[inline]
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fn load_sound_timer(&mut self, x: Reg) {
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fn store_sound_timer(&mut self, x: Reg) {
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self.sound = self.v[x];
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}
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/// Fx1e: Add vX to I,
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@ -749,7 +774,7 @@ impl CPU {
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/// I += vX;
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/// ```
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#[inline]
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fn add_to_indirect(&mut self, x: Reg) {
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fn add_i(&mut self, x: Reg) {
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self.i += self.v[x] as u16;
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}
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/// Fx29: Load sprite for character x into I
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@ -757,20 +782,24 @@ impl CPU {
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/// I = sprite(X);
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/// ```
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#[inline]
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fn load_sprite_x(&mut self, x: Reg) {
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fn load_sprite(&mut self, x: Reg) {
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self.i = self.font + (5 * (self.v[x] as Adr % 0x10));
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}
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/// Fx33: BCD convert X into I`[0..3]`
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#[inline]
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fn bcd_convert_i(&mut self, x: Reg, bus: &mut Bus) {
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fn bcd_convert(&mut self, x: Reg, bus: &mut Bus) {
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let x = self.v[x];
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bus.write(self.i.wrapping_add(2), x % 10);
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bus.write(self.i.wrapping_add(1), x / 10 % 10);
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bus.write(self.i, x / 100 % 10);
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}
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/// Fx55: DMA Stor from I to registers 0..X
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///
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/// # Authenticity
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/// The original chip-8 interpreter uses I to directly index memory,
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/// with the side effect of leaving I as I+X+1 after the transfer is done.
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#[inline]
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fn dma_store(&mut self, x: Reg, bus: &mut Bus) {
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fn store_dma(&mut self, x: Reg, bus: &mut Bus) {
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let i = self.i as usize;
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for (reg, value) in bus
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.get_mut(i..=i + x)
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@ -785,8 +814,12 @@ impl CPU {
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}
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}
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/// Fx65: DMA Load from I to registers 0..X
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///
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/// # Authenticity
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/// The original chip-8 interpreter uses I to directly index memory,
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/// with the side effect of leaving I as I+X+1 after the transfer is done.
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#[inline]
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fn dma_load(&mut self, x: Reg, bus: &mut Bus) {
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fn load_dma(&mut self, x: Reg, bus: &mut Bus) {
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let i = self.i as usize;
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for (reg, value) in bus
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.get(i + 0..=i + x)
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