60 lines
1.7 KiB
Plaintext
60 lines
1.7 KiB
Plaintext
Game Boy audio register descriptions
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NR_0 NR_1 NR_2 NR_3 NR_4 addresses
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7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
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NR1_: _ P P P D I I I d d L L L L L L V V V V E p p p l l l l l l l l T e _ _ _ h h h 0x10..0x15
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NR2_: _ _ _ _ _ _ _ _ d d L L L L L L V V V V E p p p l l l l l l l l T e _ _ _ h h h 0x15..0x1a
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NR3_: A _ _ _ _ _ _ _ L L L L L L L L _ V V _ _ _ _ _ l l l l l l l l T e _ _ _ h h h 0x1a..0x20
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NR4_: _ _ _ _ _ _ _ _ _ _ L L L L L L V V V V E p p p S S S S W c c c T e _ _ _ _ _ _ 0x20..0x25
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Comb: A P P P D I I I L L L L L L L L V V V V E p p p l l l l l l l l T e _ _ _ h h h
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d d S S S S W c c c
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Key:
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A: DAC Enable
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P: Sweep Pace
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D: Sweep Direction
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I: Sweep Individual step
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d: Duty Cycle
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L: Length Timer Initialization Value
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V: Envelope Volume Initialization Value
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E: Envelope Direction
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p: Envelope Pace
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l: Period Low Byte
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S: Clock Shift
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W: LFSR Width
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c: Clock Divider
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T: Trigger
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e: Length Enable
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h: Period High Bits
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Analog Pipeline Control Registers:
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NR_0 NR_1 NR_2 NR_3 NR_4
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7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
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NR5_: Z L L L z R R R V W X Y v w x y P _ _ _ A B C D
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Key:
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Zz: Channel 5 (VIN) Left and right sound panning
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Vv: Channel 1 Left and right sound panning
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Ww: Channel 2 Left and right sound panning
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Xx: Channel 3 Left and right sound panning
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Yy: Channel 4 Left and right sound panning
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P: APU power
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A: Channel 1 status
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B: Channel 2 status
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C: Channel 3 status
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D: Channel 4 status
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Source:
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https://gbdev.io/pandocs/Audio_Registers.html
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