Move graphics and audio out of lib.rs
This commit is contained in:
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c5490780ca
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b91105bbd1
134
src/audio.rs
Normal file
134
src/audio.rs
Normal file
@ -0,0 +1,134 @@
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use crate::memory::io::BusIO;
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use bitfield_struct::bitfield;
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#[derive(Debug, Default)]
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pub struct APU {
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regs: [u8; 0x20],
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wave: [u8; 0x10],
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amc: AMC,
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pan: SndPan,
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vol: Vol,
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}
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impl BusIO for APU {
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fn read(&self, addr: usize) -> Option<u8> {
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match addr {
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0xff10..=0xff23 => self.regs.read(addr - 0xff10),
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// 0xff10 => todo!("Channel 1 sweep"),
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// 0xff11 => todo!("Channel 1 length timer & duty cycle"),
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// 0xff12 => todo!("Channel 1 volume & envelope"),
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// 0xff13 => todo!("Channel 1 period low [write-only]"),
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// 0xff14 => todo!("Channel 1 period high & control [trigger, length enable, period]"),
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0xff24 => Some(self.vol.into_bits()),
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0xff25 => Some(self.pan.into_bits()),
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0xff26 => Some(self.amc.into_bits()),
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0xff30..=0xff3f => self.wave.read(addr - 0xff30),
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0xff76 => todo!("PCM12"),
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0xff77 => todo!("PCM34"),
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_ => None,
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}
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}
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fn write(&mut self, addr: usize, data: u8) -> Option<()> {
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#[allow(clippy::unit_arg)]
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match addr {
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0xff10..0xff14 => todo!("Channel 1"),
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0xff16..=0xff19 => todo!("Channel 2"),
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0xff1a..=0xff1e => todo!("Channel 3"),
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0xff20..=0xff23 => todo!("Channel 4"),
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0xff24 => Some(self.vol = Vol::from_bits(data)),
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// Sound panning
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0xff25 => Some(self.pan = SndPan::from_bits(data)),
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// Audio Master Control
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0xff26 => Some(self.amc.set_power(data & 0x80 != 0)),
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// Wave table memory
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0xff30..=0xff3f => self.wave.write(addr - 0xff30, data),
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0xff76 => todo!("PCM12"),
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0xff77 => todo!("PCM34"),
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_ => None,
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}
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}
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}
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#[derive(Debug, Default)]
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pub struct Channel {
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pub period: u16,
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pub duty_step: u8,
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}
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#[bitfield(u8)]
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/// Audio Master Control register
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pub struct AMC {
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/// Set when CH1 is playing. Read-only.
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ch1_on: bool,
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/// Set when CH2 is playing. Read-only.
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ch2_on: bool,
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/// Set when CH3 is playing. Read-only.
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ch3_on: bool,
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/// Set when CH4 is playing. Read-only.
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ch4_on: bool,
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#[bits(3)] // 3 bits are unused
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_reserved: (),
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/// If false, all channels are muted. Read-writable.
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power: bool,
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}
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#[bitfield(u8)]
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/// Sound Panning register. Setting `cNS` to true will send channel `N` to speaker `S`
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pub struct SndPan {
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c1r: bool,
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c2r: bool,
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c3r: bool,
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c4r: bool,
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c1l: bool,
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c2l: bool,
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c3l: bool,
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c4l: bool,
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}
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#[bitfield(u8)]
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/// Volume control and VIN panning register
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pub struct Vol {
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#[bits(3)]
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/// The volume of the right output
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right: u8,
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/// Whether VIN is sent to the right output
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vin_right: bool,
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#[bits(3)]
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/// The volume of the left output
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left: u8,
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/// Whether VIN is sent to the left output
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vin_left: bool,
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}
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pub mod channels {
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// TODO: remove
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#![allow(dead_code)]
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//! Channel controllers. Each channel controller has a function that takes a bus and outputs
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static WAVES: [[u8; 8]; 4] = [
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[0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 0xf],
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[0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0x0, 0x0],
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[0xf, 0xf, 0xf, 0xf, 0x0, 0x0, 0x0, 0x0],
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[0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xf, 0xf],
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];
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#[derive(Debug, Default)]
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pub struct Pulse {
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/// Ticks up from the initial value, and triggers a duty step when it reaches 0x800
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period: u16,
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duty_step: u8,
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duty_cycle: u8,
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output: u8,
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}
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impl Pulse {
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pub fn tick(&mut self) {
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self.period += 1;
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if self.period > 0x7ff {
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// move the duty step
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self.duty_step = (self.duty_step + 1) % 8;
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}
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}
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}
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}
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232
src/graphics.rs
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232
src/graphics.rs
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@ -0,0 +1,232 @@
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use bitfield_struct::bitfield;
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use crate::memory::io::BusIO;
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use std::mem::size_of;
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/// The number of OAM entries supported by the PPU (on real hardware, 40)
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pub const NUM_OAM_ENTRIES: usize = 40;
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#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub enum Mode {
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HBlank,
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VBlank,
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OAMScan,
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Drawing,
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}
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impl Mode {
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const fn from_bits(value: u8) -> Self {
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match value & 3 {
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0b00 => Self::HBlank,
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0b01 => Self::VBlank,
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0b10 => Self::OAMScan,
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0b11 => Self::Drawing,
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_ => unreachable!(),
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}
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}
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const fn into_bits(self) -> u8 {
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self as _
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}
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}
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type OAMTable = [OAMEntry; NUM_OAM_ENTRIES];
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#[derive(Clone, Debug, PartialEq, PartialOrd)]
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pub struct PPU {
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lcdc: LcdC, // LCD Control
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stat: Stat, // LCD Status
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scy: u8, // viewport y coordinate
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scx: u8, // viewport x coordinate
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/// Current line. Read-only.
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ly: u8, // holds values in range 0..=153 (144..=153 = vblank)
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/// Line Y for Comparison. Triggers interrupt if enabled in `stat`
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lyc: u8, // line y compare, triggers interrupt if enabled
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oam: OAMTable,
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}
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impl PPU {
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pub fn oam(&self) -> &[u8] {
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let data = self.oam.as_slice().as_ptr().cast();
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let len = size_of::<OAMTable>();
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// SAFETY:
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// [OAMEntry; NUM_OAM_ENTRIES] is sizeof<OAM_ENTRY> * NUM_OAM_ENTRIES long,
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// and already aligned
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unsafe { core::slice::from_raw_parts(data, len) }
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}
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pub fn oam_mut(&mut self) -> &mut [u8] {
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let data = self.oam.as_mut_slice().as_mut_ptr().cast();
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let len = size_of::<OAMTable>();
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// SAFETY: see above
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unsafe { core::slice::from_raw_parts_mut(data, len) }
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}
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/// Gets the current PPU operating mode
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pub fn mode(&self) -> Mode {
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self.stat.mode()
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}
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pub fn set_mode(&mut self, mode: Mode) {
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self.stat.set_mode(mode);
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}
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/// Gets the STAT interrupt selection config.
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///
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/// | Bit | Name |
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/// |:---:|:---------------|
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/// | `0` | H Blank |
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/// | `1` | V Blank |
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/// | `2` | OAM Scan |
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/// | `3` | LY Coincidence |
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pub fn stat_interrupt_selection(&self) -> u8 {
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(self.stat.into_bits() & 0b1111000) >> 3
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}
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/// Gets the LY coincidence flag. Should be true when LY = LYC
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pub fn ly_coincidence(&self) -> bool {
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self.stat.lyc_hit()
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}
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}
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impl Default for PPU {
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fn default() -> Self {
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Self {
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lcdc: Default::default(),
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stat: Default::default(),
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scy: Default::default(),
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scx: Default::default(),
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ly: Default::default(),
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lyc: Default::default(),
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oam: [Default::default(); NUM_OAM_ENTRIES],
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}
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}
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}
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impl BusIO for PPU {
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fn read(&self, addr: usize) -> Option<u8> {
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match addr {
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0xfe00..=0xfe9f => self.oam().read(addr - 0xfe00),
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0xff40 => Some(self.lcdc.into_bits()),
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0xff41 => Some(self.stat.into_bits()),
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0xff42 => Some(self.scy),
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0xff43 => Some(self.scx),
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0xff44 => Some(self.ly),
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0xff45 => Some(self.lyc),
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_ => None,
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}
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}
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fn write(&mut self, addr: usize, data: u8) -> Option<()> {
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match addr {
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0xfe00..=0xfe9f => self.oam_mut().write(addr - 0xfe00, data),
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0xff40 => Some(self.lcdc = LcdC::from_bits(data)),
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0xff41 => Some(self.stat.set_interrupts(Stat::from_bits(data).interrupts())),
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0xff42 => Some(self.scy = data),
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0xff43 => Some(self.scx = data),
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0xff44 => None,
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0xff45 => Some(self.lyc = data),
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_ => None,
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}
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}
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}
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#[repr(C)]
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#[derive(Clone, Copy, Debug, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct OAMEntry {
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y: u8, // y coordinate of the bottom of a 16px sprite
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x: u8, // x coordinate of the right of an 8px sprite
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tid: u8, // tile identifier
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attr: OAMAttr, // OAM Attributes
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}
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#[bitfield(u8)]
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/// OAM Attributes. Read-writable by CPU, read-only by PPU.
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#[derive(PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct OAMAttr {
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#[bits(3)]
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/// Which palette (OBP 0-7) does this object use in CGB mode?
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cgb_palette: u8,
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#[bits(1)]
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/// Which VRAM bank (0-1) contains this object's tile?
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cgb_bank: u8,
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#[bits(1)]
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/// Which palette (OBP 0-1) does this object use in DMG mode?
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dmg_palette: u8,
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/// Is this sprite flipped horizontally?
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x_flip: bool,
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/// Is this sprite flipped vertically?
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y_flip: bool,
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/// Is this sprite drawn below the window and background layers?
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priority: bool,
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}
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#[bitfield(u8)]
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/// LCD main control register
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#[derive(PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct LcdC {
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/// In DMG mode, disables Window and Background layers.
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/// In CGB mode, causes objects to render on top of Window and Background layers
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bg_window_enable_or_priority: bool,
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/// Controls whether objects are rendered or not
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obj_enable: bool,
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/// Controls the height of objects: false = 8px tall, true = 16px tall
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obj_size: bool,
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/// Controls bit 10 of the backgroud tile map address (false, true) => (0x9800, 0x9c00)
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bg_tile_map_area: bool,
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/// Controls which addressing mode to use when picking tiles for the window and background layers
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bg_window_tile_data_area: bool,
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/// Enables or disables the window
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window_enable: bool,
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/// Controls bit 10 of the window tile map address (false, true) => (0x9800, 0x9c00)
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window_tile_map_area: bool,
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/// Controls whether the LCD/PPU recieves power
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lcd_ppu_enable: bool,
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}
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#[bitfield(u8)]
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/// LCD Status and Interrupt Control register
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#[derive(PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub struct Stat {
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#[bits(2)]
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/// The current PPU operating [Mode]
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mode: Mode,
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/// Set to true when LYC == LY. Read only.
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lyc_hit: bool,
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#[bits(4)]
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/// Configures PPU to raise IRQ when a condition is met
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interrupts: Interrupts,
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#[bits(default = true)]
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_reserved: bool,
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}
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#[bitfield(u8)]
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/// [Stat] register interrupt configuration
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pub struct Interrupts {
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/// Configures PPU to raise IRQ on VBlank start
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hblank: bool,
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/// Configures PPU to raise IRQ on VBlank start
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vblank: bool,
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/// Configures PPU to raise IRQ on OAM Scan start
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oam: bool,
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/// Configures PPU to raise IRQ on rising edge of [lyc_hit](Stat::lyc_hit)
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lyc: bool,
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#[bits(4)]
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_unused: (),
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}
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#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub enum DMGColor {
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White,
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LGray,
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DGray,
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Black,
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}
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impl DMGColor {
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pub const fn from_bits(value: u8) -> Self {
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match value & 3 {
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0 => DMGColor::White,
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1 => DMGColor::LGray,
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2 => DMGColor::DGray,
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3 => DMGColor::Black,
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_ => unreachable!(),
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}
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}
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pub const fn to_bits(self) -> u8 {
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self as _
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}
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}
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328
src/lib.rs
328
src/lib.rs
@ -59,335 +59,11 @@ pub mod error {
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pub mod memory;
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pub mod graphics {
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use bitfield_struct::bitfield;
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use crate::memory::io::BusIO;
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use std::mem::size_of;
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/// The number of OAM entries supported by the PPU (on real hardware, 40)
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pub const NUM_OAM_ENTRIES: usize = 40;
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#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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pub enum Mode {
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HBlank,
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VBlank,
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OAMScan,
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Drawing,
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}
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impl Mode {
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const fn from_bits(value: u8) -> Self {
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match value & 3 {
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0b00 => Self::HBlank,
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0b01 => Self::VBlank,
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0b10 => Self::OAMScan,
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0b11 => Self::Drawing,
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_ => unreachable!(),
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}
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}
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const fn into_bits(self) -> u8 {
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self as _
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}
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}
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type OAMTable = [OAMEntry; NUM_OAM_ENTRIES];
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#[derive(Clone, Debug, PartialEq, PartialOrd)]
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pub struct PPU {
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lcdc: LcdC, // LCD Control
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stat: Stat, // LCD Status
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scy: u8, // viewport y coordinate
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scx: u8, // viewport x coordinate
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/// Current line. Read-only.
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ly: u8, // holds values in range 0..=153 (144..=153 = vblank)
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/// Line Y for Comparison. Triggers interrupt if enabled in `stat`
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lyc: u8, // line y compare, triggers interrupt if enabled
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oam: OAMTable,
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}
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impl PPU {
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pub fn oam(&self) -> &[u8] {
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let data = self.oam.as_slice().as_ptr().cast();
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let len = size_of::<OAMTable>();
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// SAFETY:
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// [OAMEntry; NUM_OAM_ENTRIES] is sizeof<OAM_ENTRY> * NUM_OAM_ENTRIES long,
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// and already aligned
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unsafe { core::slice::from_raw_parts(data, len) }
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}
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pub fn oam_mut(&mut self) -> &mut [u8] {
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let data = self.oam.as_mut_slice().as_mut_ptr().cast();
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let len = size_of::<OAMTable>();
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// SAFETY: see above
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unsafe { core::slice::from_raw_parts_mut(data, len) }
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}
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/// Gets the current PPU operating mode
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pub fn mode(&self) -> Mode {
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self.stat.mode()
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}
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pub fn set_mode(&mut self, mode: Mode) {
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self.stat.set_mode(mode);
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}
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/// Gets the STAT interrupt selection config.
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///
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/// | Bit | Name |
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/// |:---:|:---------------|
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/// | `0` | H Blank |
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/// | `1` | V Blank |
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/// | `2` | OAM Scan |
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/// | `3` | LY Coincidence |
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pub fn stat_interrupt_selection(&self) -> u8 {
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(self.stat.into_bits() & 0b1111000) >> 3
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}
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/// Gets the LY coincidence flag. Should be true when LY = LYC
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pub fn ly_coincidence(&self) -> bool {
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self.stat.lyc_hit()
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}
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}
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impl Default for PPU {
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fn default() -> Self {
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Self {
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lcdc: Default::default(),
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stat: Default::default(),
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scy: Default::default(),
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scx: Default::default(),
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ly: Default::default(),
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lyc: Default::default(),
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||||
oam: [Default::default(); NUM_OAM_ENTRIES],
|
||||
}
|
||||
}
|
||||
}
|
||||
impl BusIO for PPU {
|
||||
fn read(&self, addr: usize) -> Option<u8> {
|
||||
match addr {
|
||||
0xfe00..=0xfe9f => self.oam().read(addr - 0xfe00),
|
||||
0xff40 => Some(self.lcdc.into_bits()),
|
||||
0xff41 => Some(self.stat.into_bits()),
|
||||
0xff42 => Some(self.scy),
|
||||
0xff43 => Some(self.scx),
|
||||
0xff44 => Some(self.ly),
|
||||
0xff45 => Some(self.lyc),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
fn write(&mut self, addr: usize, data: u8) -> Option<()> {
|
||||
match addr {
|
||||
0xfe00..=0xfe9f => self.oam_mut().write(addr - 0xfe00, data),
|
||||
0xff40 => Some(self.lcdc = LcdC::from_bits(data)),
|
||||
0xff41 => Some(self.stat.set_interrupts(Stat::from_bits(data).interrupts())),
|
||||
0xff42 => Some(self.scy = data),
|
||||
0xff43 => Some(self.scx = data),
|
||||
0xff44 => None,
|
||||
0xff45 => Some(self.lyc = data),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[repr(C)]
|
||||
#[derive(Clone, Copy, Debug, Default, PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct OAMEntry {
|
||||
y: u8, // y coordinate of the bottom of a 16px sprite
|
||||
x: u8, // x coordinate of the right of an 8px sprite
|
||||
tid: u8, // tile identifier
|
||||
attr: OAMAttr, // OAM Attributes
|
||||
}
|
||||
|
||||
#[bitfield(u8)]
|
||||
/// OAM Attributes. Read-writable by CPU, read-only by PPU.
|
||||
#[derive(PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct OAMAttr {
|
||||
#[bits(3)]
|
||||
/// Which palette (OBP 0-7) does this object use in CGB mode?
|
||||
cgb_palette: u8,
|
||||
#[bits(1)]
|
||||
/// Which VRAM bank (0-1) contains this object's tile?
|
||||
cgb_bank: u8,
|
||||
#[bits(1)]
|
||||
/// Which palette (OBP 0-1) does this object use in DMG mode?
|
||||
dmg_palette: u8,
|
||||
/// Is this sprite flipped horizontally?
|
||||
x_flip: bool,
|
||||
/// Is this sprite flipped vertically?
|
||||
y_flip: bool,
|
||||
/// Is this sprite drawn below the window and background layers?
|
||||
priority: bool,
|
||||
}
|
||||
|
||||
#[bitfield(u8)]
|
||||
/// LCD main control register
|
||||
#[derive(PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct LcdC {
|
||||
/// In DMG mode, disables Window and Background layers.
|
||||
/// In CGB mode, causes objects to render on top of Window and Background layers
|
||||
bg_window_enable_or_priority: bool,
|
||||
/// Controls whether objects are rendered or not
|
||||
obj_enable: bool,
|
||||
/// Controls the height of objects: false = 8px tall, true = 16px tall
|
||||
obj_size: bool,
|
||||
/// Controls bit 10 of the backgroud tile map address (false, true) => (0x9800, 0x9c00)
|
||||
bg_tile_map_area: bool,
|
||||
/// Controls which addressing mode to use when picking tiles for the window and background layers
|
||||
bg_window_tile_data_area: bool,
|
||||
/// Enables or disables the window
|
||||
window_enable: bool,
|
||||
/// Controls bit 10 of the window tile map address (false, true) => (0x9800, 0x9c00)
|
||||
window_tile_map_area: bool,
|
||||
/// Controls whether the LCD/PPU recieves power
|
||||
lcd_ppu_enable: bool,
|
||||
}
|
||||
|
||||
#[bitfield(u8)]
|
||||
/// LCD Status and Interrupt Control register
|
||||
#[derive(PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub struct Stat {
|
||||
#[bits(2)]
|
||||
/// The current PPU operating [Mode]
|
||||
mode: Mode,
|
||||
/// Set to true when LYC == LY. Read only.
|
||||
lyc_hit: bool,
|
||||
#[bits(4)]
|
||||
/// Configures PPU to raise IRQ when a condition is met
|
||||
interrupts: Interrupts,
|
||||
#[bits(default = true)]
|
||||
_reserved: bool,
|
||||
}
|
||||
|
||||
#[bitfield(u8)]
|
||||
/// [Stat] register interrupt configuration
|
||||
pub struct Interrupts {
|
||||
/// Configures PPU to raise IRQ on VBlank start
|
||||
hblank: bool,
|
||||
/// Configures PPU to raise IRQ on VBlank start
|
||||
vblank: bool,
|
||||
/// Configures PPU to raise IRQ on OAM Scan start
|
||||
oam: bool,
|
||||
/// Configures PPU to raise IRQ on rising edge of [lyc_hit](Stat::lyc_hit)
|
||||
lyc: bool,
|
||||
#[bits(4)]
|
||||
_unused: (),
|
||||
}
|
||||
|
||||
#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
|
||||
pub enum DMGColor {
|
||||
White,
|
||||
LGray,
|
||||
DGray,
|
||||
Black,
|
||||
}
|
||||
|
||||
impl DMGColor {
|
||||
pub const fn from_bits(value: u8) -> Self {
|
||||
match value & 3 {
|
||||
0 => DMGColor::White,
|
||||
1 => DMGColor::LGray,
|
||||
2 => DMGColor::DGray,
|
||||
3 => DMGColor::Black,
|
||||
_ => unreachable!(),
|
||||
}
|
||||
}
|
||||
pub const fn to_bits(self) -> u8 {
|
||||
self as _
|
||||
}
|
||||
}
|
||||
}
|
||||
pub mod graphics;
|
||||
|
||||
pub mod cpu;
|
||||
|
||||
pub mod audio {
|
||||
use crate::memory::io::BusIO;
|
||||
use bitfield_struct::bitfield;
|
||||
|
||||
#[derive(Debug, Default)]
|
||||
pub struct APU {
|
||||
wave: [u8; 0x10],
|
||||
amc: AMC,
|
||||
pan: SndPan,
|
||||
vol: Vol,
|
||||
}
|
||||
|
||||
impl BusIO for APU {
|
||||
fn read(&self, addr: usize) -> Option<u8> {
|
||||
match addr {
|
||||
0xff10 => todo!("Channel 1 sweep"),
|
||||
0xff11 => todo!("Channel 1 length timer & duty cycle"),
|
||||
0xff12 => todo!("Channel 1 volume & envelope"),
|
||||
0xff13 => todo!("Channel 1 period low [write-only]"),
|
||||
0xff14 => todo!("Channel 1 period high & control [trigger, length enable, period]"),
|
||||
0xff24 => Some(self.vol.into_bits()),
|
||||
0xff25 => Some(self.pan.into_bits()),
|
||||
0xff26 => Some(self.amc.into_bits()),
|
||||
0xff30..=0xff3f => self.wave.read(addr - 0xff30),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
|
||||
fn write(&mut self, addr: usize, data: u8) -> Option<()> {
|
||||
#[allow(clippy::unit_arg)]
|
||||
match addr {
|
||||
0xff10..=0xff14 => todo!("Channel 1"),
|
||||
0xff16..=0xff19 => todo!("Channel 2"),
|
||||
0xff1a..=0xff1e => todo!("Channel 3"),
|
||||
0xff20..=0xff23 => todo!("Channel 4"),
|
||||
0xff24 => Some(self.vol = Vol::from_bits(data)),
|
||||
// Sound panning
|
||||
0xff25 => Some(self.pan = SndPan::from_bits(data)),
|
||||
// Audio Master Control
|
||||
0xff26 => Some(self.amc.set_power(data & 0x80 != 0)),
|
||||
// Wave table memory
|
||||
0xff30..=0xff3f => self.wave.write(addr - 0xff30, data),
|
||||
_ => None,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[bitfield(u8)]
|
||||
/// Audio Master Control register
|
||||
pub struct AMC {
|
||||
/// Set when CH1 is playing. Read-only.
|
||||
ch1_on: bool,
|
||||
/// Set when CH2 is playing. Read-only.
|
||||
ch2_on: bool,
|
||||
/// Set when CH3 is playing. Read-only.
|
||||
ch3_on: bool,
|
||||
/// Set when CH4 is playing. Read-only.
|
||||
ch4_on: bool,
|
||||
#[bits(3)] // 3 bits are unused
|
||||
_reserved: (),
|
||||
/// If false, all channels are muted. Read-writable.
|
||||
power: bool,
|
||||
}
|
||||
|
||||
#[bitfield(u8)]
|
||||
/// Sound Panning register. Setting `cNS` to true will send channel `N` to speaker `S`
|
||||
pub struct SndPan {
|
||||
c1r: bool,
|
||||
c2r: bool,
|
||||
c3r: bool,
|
||||
c4r: bool,
|
||||
c1l: bool,
|
||||
c2l: bool,
|
||||
c3l: bool,
|
||||
c4l: bool,
|
||||
}
|
||||
|
||||
#[bitfield(u8)]
|
||||
/// Volume control and VIN panning register
|
||||
pub struct Vol {
|
||||
#[bits(3)]
|
||||
/// The volume of the right output
|
||||
right: u8,
|
||||
/// Whether VIN is sent to the right output
|
||||
vin_right: bool,
|
||||
#[bits(3)]
|
||||
/// The volume of the left output
|
||||
left: u8,
|
||||
/// Whether VIN is sent to the left output
|
||||
vin_left: bool,
|
||||
}
|
||||
}
|
||||
pub mod audio;
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user