Fix some bugs in memory
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8e97961955
commit
3d35fe8ae7
206
src/memory.rs
206
src/memory.rs
@ -19,7 +19,6 @@
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use self::{
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banked::{Banked, UpperBanked},
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io::BusIO,
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mapper::Mapper,
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};
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pub mod banked;
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pub mod io;
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@ -44,25 +43,21 @@ impl Mode {
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}
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}
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/// The [Bus] controls the memory map from the CPU's perspective
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#[derive(Debug)]
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pub struct Bus {
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mode: Mode,
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// TODO: define a way to have an arbitrary memory map
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// TODO: Replace the cart entirely
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// TODO: Separate into external and vram bus
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// TODO: Implement multiple views into memory
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cart: Cart,
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// VRAM is a 0x2000 B window from 0x8000..0xa000, with two banks
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vram: Banked<0x8000, 0x2000, 2>,
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// WRAM is a 0x2000 B window from 0xc000..0xe000. The upper half is banked.
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wram: UpperBanked<0xc000, 0x1000, 8>,
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// Memory mapped IO registers, HRAM
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// HRAM is a 0x80 B window from 0xff80..0xffff
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hram: [u8; 0x80],
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// Joypad driver
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// Serial driver
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// Timer and divider
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// Interrupt controller
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// Audio controller
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// PPU/LCD controller
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mmio: [u8; 0x80],
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//
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hmem: [u8; 0x100],
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}
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impl BusIO for Bus {
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@ -82,10 +77,7 @@ impl BusIO for Bus {
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0xfe00..=0xfe9f => Some(0x0a),
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// Illegal
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0xfea0..=0xfeff => None,
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// Memory mapped IO
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0xff00..=0xff7f => self.mmio.read(addr & 0x7f),
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// HiRAM
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0xff80..=0xffff => self.hram.read(addr & 0x7f),
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0xff00..=0xffff => self.hmem.read(addr & 0xff),
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_ => None,
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}
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}
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@ -106,10 +98,8 @@ impl BusIO for Bus {
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0xfe00..=0xfe9f => Some(()),
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// Illegal
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0xfea0..=0xfeff => None,
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// Memory mapped IO
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0xff00..=0xff7f => self.mmio.write(addr & 0x7f, data),
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// HiRAM
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0xff80..=0xffff => self.hram.write(addr & 0x7f, data),
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// Memory mapped IO & HRAM
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0xff00..=0xffff => self.hmem.write(addr & 0xff, data),
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_ => None,
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}
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}
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@ -122,8 +112,7 @@ impl Bus {
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mode: Mode::CGB,
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vram: Default::default(),
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wram: Default::default(),
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mmio: [0; 128],
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hram: [0; 128],
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hmem: [0; 256],
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}
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}
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@ -156,7 +145,7 @@ impl Bus {
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Mode::DMG => {}
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},
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}
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self.mmio.get(addr % 0x80).copied()
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self.hmem.get(addr % 0x80 + 0x80).copied()
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}
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pub fn mmio_read_cgb(&self, addr: usize) -> Option<u8> {
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@ -209,7 +198,7 @@ impl Bus {
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Mode::DMG => {}
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},
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}
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self.mmio.write(addr % 0x80, data)
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self.hmem.write(addr % 0x80 + 0x80, data)
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}
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pub fn mmio_write_cgb(&mut self, addr: usize, data: u8) -> Option<()> {
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@ -242,17 +231,22 @@ impl Bus {
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}
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}
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pub use cart::Cart;
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mod cart {
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use super::{mapper::*, BusIO};
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use crate::{
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constants::{RAM_BANK, ROM_BANK},
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memory::io::BusAux,
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};
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use std::fmt::Debug;
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pub struct Cart {
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pub rom: Vec<u8>,
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pub ram: Vec<u8>,
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mapper: Box<dyn Mapper>,
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mapper: MBC,
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}
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mod cart {
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use crate::memory::io::BusAux;
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use super::{mapper::*, BusIO, Cart};
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use std::fmt::Debug;
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impl BusIO for Cart {
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fn read(&self, addr: usize) -> Option<u8> {
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match self.mapper.read(addr) {
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@ -276,23 +270,28 @@ mod cart {
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}
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/// Read cartridge header, as defined in the [Pan docs](https://gbdev.io/pandocs/The_Cartridge_Header.html)
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impl Cart {
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pub fn new(rom: Vec<u8>) -> Self {
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let rom_size = rom.romsize().expect("ROM should have cart header!");
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let ram_size = rom.ramsize().expect("ROM should have cart header!");
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pub fn new(mut rom: Vec<u8>, mut ram: Vec<u8>) -> Self {
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let rom_size = ROM_BANK * rom.romsize().expect("ROM should have cart header!");
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let ram_size = RAM_BANK * rom.ramsize().expect("ROM should have cart header!");
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if rom_size > rom.len() {
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eprintln!("Rom claims to be {rom_size}, but is actually {}", rom.len());
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}
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rom.resize(rom_size, 0);
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ram.resize(ram_size, 0);
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let cart_type = rom.carttype().expect("ROM should have cart header!");
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Self {
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mapper: match cart_type {
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0 => Box::<no_mbc::NoMBC>::default(),
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1 => Box::new(mbc1::MBC1::new(rom_size, 0)), // ROM
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2 => Box::new(mbc1::MBC1::new(rom_size, ram_size)), // ROM + RAM
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3 => Box::new(mbc1::MBC1::new(rom_size, ram_size)), // ROM + RAM + Battery
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// _ => Box::<NoMBC>::default(),
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n => todo!("Mapper 0x{n:02x}"),
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},
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mapper: MBC::from_cart_type(cart_type).expect("MAPPER NOT FOUND: {cart_type}"),
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rom,
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ram: vec![],
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ram,
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}
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}
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pub fn load_save(&mut self, save: &[u8]) {
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self.ram.resize(save.len(), 0);
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self.ram.copy_from_slice(save)
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}
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}
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impl Debug for Cart {
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@ -306,19 +305,19 @@ mod cart {
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impl From<Vec<u8>> for Cart {
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fn from(value: Vec<u8>) -> Self {
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Self::new(value)
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Self::new(value, vec![])
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}
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}
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impl From<&[u8]> for Cart {
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fn from(value: &[u8]) -> Self {
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Self::new(Vec::from(value))
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Self::new(Vec::from(value), vec![])
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}
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}
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impl<Item: AsRef<u8>> FromIterator<Item> for Cart {
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fn from_iter<T: IntoIterator<Item = Item>>(iter: T) -> Self {
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Self::new(iter.into_iter().map(|item| *(item.as_ref())).collect())
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Self::new(iter.into_iter().map(|item| *(item.as_ref())).collect(), vec![])
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}
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}
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@ -368,6 +367,48 @@ pub mod mapper {
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fn write(&mut self, addr: usize, val: u8) -> Response;
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}
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pub enum MBC {
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None,
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MBC1(mbc1::MBC1),
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// TODO: MBC2, 3, 5
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}
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impl MBC {
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pub fn from_cart_type(cart_type: u8) -> Option<Self> {
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Some(match cart_type {
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0 => Self::None,
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1 => Self::MBC1(mbc1::MBC1::new()), // ROM
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2 => Self::MBC1(mbc1::MBC1::new()), // ROM + RAM
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3 => Self::MBC1(mbc1::MBC1::new()), // ROM + RAM + Battery
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n => {
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eprintln!("Mapper 0x{n:02x}");
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None?
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}
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})
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}
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pub fn read(&self, addr: usize) -> Response {
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match self {
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MBC::None => match addr {
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0x0000..=0x7fff => Response::Rom(addr),
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0xa000..=0xbfff => Response::Ram(addr - 0xa000),
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_ => Response::None,
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},
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MBC::MBC1(mbc) => mbc.read(addr),
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}
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}
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pub fn write(&mut self, addr: usize, val: u8) -> Response {
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match self {
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MBC::None => match addr {
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0xa000..=0xbfff => Response::Ram(addr),
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_ => Response::None,
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},
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MBC::MBC1(mbc) => mbc.write(addr, val),
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}
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}
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}
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pub mod no_mbc {
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use super::*;
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@ -378,14 +419,14 @@ pub mod mapper {
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fn read(&self, addr: usize) -> Response {
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match addr {
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0x0000..=0x7fff => Response::Rom(addr),
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0xa000..=0xbfff => Response::Ram(addr - 0x8000),
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0xa000..=0xbfff => Response::Ram(addr - 0xa000),
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_ => Response::None,
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}
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}
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fn write(&mut self, addr: usize, _val: u8) -> Response {
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match addr {
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0xa000..=0xbfff => Response::Ram(addr - 0xA000),
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0xa000..=0xbfff => Response::Ram(addr - 0xa000),
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_ => Response::None,
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}
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}
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@ -394,71 +435,66 @@ pub mod mapper {
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pub mod mbc1 {
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use super::*;
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use crate::constants::*;
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#[derive(Clone, Copy, Debug, Default)]
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pub struct MBC1 {
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rom_mask: u8,
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ram_mask: u8,
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mode: u8,
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rom_bank: u8,
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ram_bank: u8,
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bank_enable: bool,
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ram_enable: bool,
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bank_lo: u8,
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bank_hi: u8,
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}
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impl MBC1 {
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pub fn new(rom_size: usize, ram_size: usize) -> Self {
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Self {
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rom_mask: (rom_size).wrapping_sub(1) as u8,
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ram_mask: (ram_size).wrapping_sub(1) as u8,
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rom_bank: 1,
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..Default::default()
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pub fn new() -> Self {
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Self { bank_lo: 1, ..Default::default() }
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}
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pub fn rom_lower(&self) -> usize {
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match self.bank_enable {
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true => ((self.bank_hi << 5) as usize) * ROM_BANK,
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false => 0,
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}
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}
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pub fn rom_bank_lower(&self) -> usize {
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(((self.ram_bank << 5) & self.rom_mask) as usize) << 14
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pub fn rom_upper(&self) -> usize {
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((self.bank_lo | (self.bank_hi << 5)) as usize) * ROM_BANK
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}
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pub fn rom_bank_upper(&self) -> usize {
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((self.rom_bank | (self.ram_bank << 5) & self.rom_mask) as usize) << 14
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pub fn ram_base(&self) -> usize {
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match self.bank_enable {
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true => (self.bank_hi as usize) * RAM_BANK,
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false => 0,
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}
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pub fn ram_bank_base(&self) -> usize {
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((self.ram_bank & self.ram_mask) as usize) << 13
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}
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}
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impl Mapper for MBC1 {
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fn read(&self, addr: usize) -> Response {
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match (addr, self.mode) {
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(0x0000..=0x3fff, 0) => Response::Rom(addr),
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(0x0000..=0x3fff, _) => Response::Rom(self.rom_bank_lower() | (addr & 0x3fff)),
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(0x4000..=0x7fff, _) => Response::Rom(self.rom_bank_upper() | (addr & 0x3fff)),
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(0xa000..=0xbfff, 0) => Response::Ram(addr & 0x1fff),
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(0xa000..=0xbfff, _) => Response::Ram(self.ram_bank_base() | (addr & 0x1fff)),
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match addr >> 12 {
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0..=3 => Response::Rom(self.rom_lower() | addr),
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4..=7 => Response::Rom(self.rom_upper() | (addr % ROM_BANK)),
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0xa | 0xb => Response::Ram(self.ram_base() | (addr % RAM_BANK)),
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_ => Response::None,
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}
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}
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fn write(&mut self, addr: usize, val: u8) -> Response {
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match (addr, self.mode) {
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(0x0000..=0x1fff, _) => {
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match addr >> 12 {
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0x0 | 0x1 => {
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self.ram_enable = val & 0xf == 0xa;
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}
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(0x2000..=0x3fff, _) => {
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self.rom_bank = (val & 0x1f).max(1);
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0x2 | 0x3 => {
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self.bank_lo = (val & 0x1f).max(1);
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}
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(0x4000..=0x5fff, _) => {
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self.ram_bank = val & 0x3;
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0x4 | 0x5 => {
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self.bank_hi = val & 0x3;
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}
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(0x6000..=0x7fff, _) => {
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self.mode = val & 1;
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0x6 | 0x7 => {
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self.bank_enable = val & 1 != 0;
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}
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(0xa000..=0xbfff, 0) if self.ram_enable => {
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return Response::Ram(addr & 0x1fff);
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}
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(0xa000..=0xbfff, 1) if self.ram_enable => {
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return Response::Ram((self.ram_bank as usize & 0b11 << 13) | addr & 0x1fff)
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0xa | 0xb if self.ram_enable => {
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return Response::Ram(self.ram_base() | (addr % RAM_BANK))
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}
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_ => return Response::None,
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}
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